Travelling On The Silicon Road

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

Yet another company exits the Structured ASIC arena. After LSI Logic and then Synplicity, it’s now the turn of NEC. This is in line with a string of closures/layoffs and policy changes announced by Mr. Nakajima, NEC’s president.

NEC feels that Structured ASICs have not grown to a big biz yet and is risky to invest large resources in it. This is further aggravated when the company itself is not doing well overall.

Why is it that Structured ASICs hasn’t caught on? The general thinking when Structured ASICs evolved was that as long as there is the issue of high NREs and long design cycle time compounded by increasing risks involved with new designs/new techno/short market window etc., there will be a need to address the gap between FPGAs and Cell based ASICs. Structured ASICs definitely address this gap.

Could a possible reasoning be in the marketing strategy of Structured ASICs ??? As some one had pointed out a few years back……”Most of the companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against FPGAs. The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines’ lowest density is close to the highest density available in FPGA, there really isn’t much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn’t often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology”