ASIC makers piece together their options

Refering to “ASIC makers piece together their options” – Ron Wilson & Brian Fuller in EE Times

In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.

But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.

The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??

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