Archive for the 'ASICs' Category

Internet of Things (IoT) and the opportunities for chip biz

Thursday, February 14th, 2013

There has been a lot of talk on Internet of Things (IoT) or Machine2Machine (M2M) communications – which basically is an intelligent grid of devices connected to each other through the internet. Chips are embedded in the devices enabling them to relay information, take decisions, communicate commands and adjust settings/implement a requisite action(s) accordingly.

As per a report from ABI Research, over five billion wireless connectivity chips will ship in 2013.

What does this mean for the chip biz?

Some basic things that various devices involved in this IoT will include are: wireless connectivity (mostly low power unless one or more of these devices is connected to the mains), sensors, MEMs and control units.

The control units here needn’t be too fancy – efficient and sufficient enough to do the task they are assigned for. They span from low end to high end depending on the computing power required for the control functions - served by MCUs, embedded processors. The sensors (for temperature, pressure, moisture, light etc.) are coupled with accelerometers, gyroscopes and the like.

Connecting to the internet – wirelessly and power efficiently – that will be the key for connectivity stake holders in this space. Nuel has come up with an interesting way to achieve this. It recently announced a white space (unused frequencies during TV channels’ transmission) radio chip for low power communications and come out with a chip to demonstrate the same (it implements the “Weightless’ specifications)

One thing I find interesting about IoT/M2M is that it does not have any defined market space/application. There are potentially several applications, several markets where these can find their way. So, while one can chose to specialize in servicing one market/application, a choice of providing a generic chip/platform (control/sensor/connectivity) for any or combination/integration (SoC) of the components of the basic fabric for any (or at least most of the applications) is also wide open.

However, for the application to catch on, it has to be implemented in an inexpensive way and should be easy to use - and that is where we’ll see some exciting innovation & integration happening

AMD acquires SeaMicro

Friday, March 2nd, 2012

AMD starts selling Intel based servers – it does make an intriguing catch phrase, correct?

AMD’s latest acquisition of SeaMicro has caused some ripples. SeaMicro is a US based exclusive start-up claiming high power and space reductions (both key factors in the server market). And it currently sells exclusively Intel based servers. Its technology includes a custom CPU (Atom or Xeon) + DRAM + Freedom Fabric ASIC.

AMD has seen its market share in the server market fall from 15% in 2007 to 6.5% in 2011. Add to it the fact that almost 22% of the company’s market share depends upon server sales. So, this acquisition will strengthen AMD’s stake in this sector.

Outlook here may well include – AMD phasing out Intel’s design/chips and replacing with its own (the thread performance of its CPUs score over Intel’s) or perhaps ARM (following its partners (IBM, Dell, HP) and…. at the mention of partners, with AMD selling chips to its existing partners and also selling servers which count these partners as competition, this acquisition can pose a channel conflict

Decline in ASIC design starts

Wednesday, December 5th, 2007

The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4 percent from 2006’s 3,408, according to market research company Gartner Inc. Of the 2007 ASIC design starts, about 200 starts made at 65-nanometer design rules or below.

A few interesting points from this report:

- In general ASIC design starts are declining. Exponentially increasing cost at leading edge plus a strong ASSP offering (which amortizes costs across multiple customers) are cited as the main factors. - Companies pushing leading-edge ASIC designs tend to be in high-performance computing, wired communications, high-end storage, high-end cellular phones and video game consoles.

- The average revenue per design and the average units per design continue to rise, resulting in overall growth in ASIC revenue.

- Designers in China are not using leading edge technologies; hence contribute to slowing of the overall ASIC start-ups’ decline.

- This also leads to China representing a market with ASIC growth potential.

- More ASIC design starts are predicted in Asia-Pac

Now, we have been talking of ASIC decline for the last 5-6 years. The question remains: is there any life left in the ASIC market? The answer is a provisional “yes.” as per  Hugh Durdan, vice president of marketing for eSilicon Corp, a fabless ASIC house and I am inclined to agree with him due to the following reasons:

- Inspite of overall decline in ASIC design starts, overall revenue is increasing. Big players like Cisco, Nortel and other major OEMs continue to use ASICs for differentiation

- While FPGAs have improved in their race to catch up (and substitute) ASICs, the gap still remains. Structured ASICs have tried to fill this gap but have had a mixed response from the industry and market. Till the industry figures out a way to address this gap, ASICs and FPGAs will co-exist

- The big ASIC players have come up with various approaches to revive this ASIC market. Some of them are:

- IBM, world’s no 2 ASIC supplier (after TI) maintains that they do not see any slow down. It rolled out its ASIC offering this year in 45nm techno which combines embedded DRAM with SOI technology. However, let me add that this is more geared towards niche & bleeding edge applications and the mainstream ASIC sector consists of products based on 130- and 90-nm technologies and the 65-nm ASIC market remains small. Also SOI is more costly than the traditional bulk silicon process and this may not help the mainstream ASIC market.

- Earlier this year, NEC Electronics rolled out the CB-55L, a cell-based ASIC technology built around a 55-nm process. Believed to be the world’s first logic device that utilizes a high-k dielectric film for the gate stack, it claims to reduce leakage current and improve power consumption by 40 percent over previous 90-nm devices

- Toshiba is readying its previously announced, 45-nm ASIC line. The technology is based on bulk CMOS, which it claims will outperform the SOI-based offering from IBM.  

CSSP: A new cross road in chip evolution

Monday, October 1st, 2007

In his editor’s note, Majeed Ahmed of EETimes, Asia comments on CSSP (Customer Specific Standard Product) as an interesting turn point.


QuickLogic has broken from its FPGA past (hard time competing with the Coke and Pepsi of FPGA world i.e. Xilinx and Altera) by coming out with CSSP – an alternative design solution integrating the “application specific” functions (akin to ASSP) while incorporating a programmable fabric which allows additional “customer specific” functionality for flexibility and differentiation.


It is indeed a mutation in the semiconductor fabric, as pointed out by Majeed and a step towards trying to address the increasing challenges of the market. However I see it is another variant of the structured ASIC technology; trying to get a foothold between flexibility and cost plus time to market


…. and too early to term it as a new cross road in chip evolution.

ESL tool targets algorithm for FPGA, ASIC devices

Wednesday, April 25th, 2007

Synplicity rolled out its Synplify DSP ASIC Edition software at the Design Automation and Test Europe conference in France. Their earlier ESL synthesis tool was aimed at FPGA designs. With this new offering, they are targeting customers who use FPGA prototyping for their DSP based ASICs.

Another recent news has been that TSMC is broadening its IP portfolio giving worries to IP providers and speculation in the industry whether TSMC is moving towards ASIC like biz model.

Gives a new meaning to the phrase “ASIC demise”………

Are ASICs dead?

Monday, March 12th, 2007

There were some very interesting insights from the commentary on the panel discussion on the above topic.

People have been long talking about the demise of ASICs….and these are still around. A good starting point taken, hence, was the definition of ASICs itself. ASICs have undergone a transformation over the years and have evolved much from the traditional cell based ASICs.

Some interesting comments raised included:

- why have ASICs survived? Inspite of ridiculous prices, extremely unreliable and extremely unpredictable. Because they are needed. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing (Sherwani/OpenSilicon)
- Architecture is the key. More integration is not necessarily the right solution (Massabki/ChipX)
- How outsourcing and offshoring of basic R&D is affecting ASIC biz (Sherwani)

When we talk about ASICs declining, what are we referring to? Is it the number of design starts? And if so, which designs does this number include: cell based ASICs, embedded array, structured ASICs? Is it the total revenue?

Without a clear definition and specific measuring criteria, blanket statements do not make much sense.

Virtual versus Vertical

Wednesday, December 21st, 2005

Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.

DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.

With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.

Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty.

ASIC makers piece together their options

Saturday, October 1st, 2005

Refering to “ASIC makers piece together their options” – Ron Wilson & Brian Fuller in EE Times

In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.

But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.

The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??

Open-Silicon automates the flow

Monday, September 19th, 2005

Refering to When infrastructure is essence: Open-Silicon automates the flow , an article posted in Electronic Engineering Times by Ron Wilson on Sep 16 2005

ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.

Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.

It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.

Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.

Advent of Program Management in ASIC implementation

Wednesday, August 17th, 2005

ASICs started getting complex. Teams got globally dispersed. This was now no longer restricted to the foundries or the chip backend operations but also to the design team. Add to that a customer sitting in another location. To get a synergy across these islands of expertise for a FTSS moved Program Management role to a necessity. A necessity highlighted by the spiraling cost of design re-spins and exacerbated by the fragmented and transient market requirements.

From my experience, here are a few enablers for successful program implementation:
- Pro-active involvement right from the beginning i.e. from RFQ evaluation.
- Clear formulation of the specs mutually agreed and signed by both vendor and client. In this transient market, modifications are inevitable. However time spent in getting the basic set right is worthwhile.
- A well defined program schedule with clear allocation of resources and checklists
and it’s effective implementation. There are many software packages in the market; however keep in mind that a tool is as good as it’s implementation
- Effective communication
In my experience, lack of effective communication has been a major source of delays and issues cropping up in the program. Technical issues and logistic problems may be sorted out with a lesser impact. And it’s not just a language difference. Cultural and personality issues are not insignificant here. Effective documentation, a good rapport, increased presence, periodic meetings & regular updates, conference calls followed up by a written summary are a few enablers here.
- Anticipate and pre-empt issues and effective workarounds/solutions for problems
A good grasp of the complete ASIC supply chain provides an excellent leverage here. A good Program Manager can foresee the implications of decisions taken in a particular program phase, e.g. design on another phase e.g. packaging, on the ASIC program; a fact which may be lost on an engineer sitting in his island of expertise.