4th June 2014

Semiconductor and Cloud

A couple of years back, I had given a talk as well as moderated a panel on chip design and cloud. I had written about the same later in one of my blog posts, Chip designing and the Cloud.

I ended the article with “In summary, cloud computing in chip design will be a big paradigm shift and is poised to bring about tremendous benefits to the design eco-system. However for the design community to actively adopt it, the relevant stakeholders need to look into it in a holistic way and much beyond the scalable and economic computing power and data storage combo. And this may very well redefine the existing chip design methodology.”

So the recent news on Silicon Cloud International bringing together ecosystem partners for chip design at DAC was quite heartening to note.

SCI establishes secure cloud computing centers for scientific and engineering applications across the world. As an initial application, SCI’s cloud is providing turn-key design-to-manufacturing semiconductor design workflows for universities and research institutions. SCI’s private cloud and thin client architecture establishes a novel security model for semiconductor ecosystem providers and users.

posted in Semiconductor, Ecosystem, Cloud, chip design | 0 Comments

28th April 2014

Mobility and IoT - and its impact on the semiconductor industry

I attended the Semicon 2014 last week here in Singapore at the Marina Bay Sands – after a self-imposed hiatus of a few years. I attribute the hiatus to Semi charging people to attend its industry tracks. I do realize that they too have to make a bit of money to sustain but then it is always tough to pay for an event once you get used to participating in them for free for some years! Anyhow, as I was chairing a session on the Fabless/IDM Technology Challenges track in this year’s event, I had free access to all its tracks and especially the market trends as well as the networking cocktail event held on the first day. The market trend has always been a big crowd puller for Semi and this year was no exception.


Anyhow, let me talk here about the Fabless/IDM track. This was co-organized by SSIA (Singapore Semiconductor Industry Association) of which I happen to be an executive committee member, along with Semi.

The theme of this track was “Mobility and IoT - and its impact on the semiconductor industry “. The growth has been quite rapid in this space especially now in the IoT one. The potential market is huge, is fragmented and with low barriers to entry and no major competitors/players (as yet) – a conducive backdrop on Porter’s five competitive forces shaping industry competition. Unlike the smartphone market which has evolved into a cut throat biz dominated by vertically integrated players, the IoT looks set to provide a refreshing levelling impetus.

We are looking into some exciting and innovating market opportunities in this space, especially on the IoT front. Apart from the potentially high growth applications markets that this opens up for the semiconductor industry, the underlying fabric of our industry is also seeing transformation at various levels including the increasing inter dependency and synergy across the various entities in this eco system. These emerging application markets and morphing industry ecosystem bring along several interesting visions and opportunities as well as new challenges. So it was with a lot of excitement and quest for knowing more on this aspect that I was looking forward to chairing this session and especially more to moderating the panel discussion following the presentations. And of course, the great speakers and the panellist line-up fuelled this up.

The speakers included Vincent Tong, SVP, New Product Introductions and Worldwide Quality & Asia Pacific Executive Leader, Xilinx, Greg Turetzky, Strategic Business Development Manager, Wireless Communication Systems Group, Intel, Jennifer Teo, VP of Manufacturing and GM, Silicon Labs International and Giuseppe Miano, VP Asia Operations and MD, Broadcom, Singapore. Vincent’s talk dwelled on IoT requiring advanced SoC with differentiation as a key i.e. differentiation with intelligence and flexibility and hence programmability. Greg spoke about ubiquitous location for all mobile platforms, the opportunities and the challenges. The market opportunities have expanded from GPS to GNSS and now to location with the latter being the next big opportunity – always located and with context. Jennifer talked about how IoT is being a game changer and dwelt on the technologies required for the “things”. Giuseppe spoke about the 3rd wave of wireless connectivity – from connecting to consumption to sensing (and controlling). Have added another acronym to my vocab – BYOW (Bring your own wearable) – and must say I find that cool! He also spoke about the favourable market dynamics driving the growth as well as the aspects that need to start being considered especially on the manufacturing, logistics and suppliers side.

The panel discussion following these talks centred on “Harnessing the power of Mobility and IoT – perspectives from the semiconductor industry”. The panellists included the earlier speakers and
Subramani Kengeri, VP, Advanced Technology Architecture, GlobalFoundries and Francis Puno, Chairman SEA Work Group of Continua Health Alliance.


With stake holders from across the value-chain – IDM, fabless, foundry, application – the panel stirred up a lively and insightful debate. While the insights were quite forthcoming on my questions regarding the technical and even the ecosystem enablers, there was almost a conspiratorial silence from the panel on my query about the biz models they anticipated to develop or emerge with IoT applications. As they said, everyone is holding their cards close to their chest!

It was an insightful and a highly engaging session where all the speakers and panelists spoke passionately about this industry. And that is always heartening!


posted in Semiconductor, Business, Fabless, Industry Events, Ecosystem, Market trend, Internet of Things, IoT, IDM | 0 Comments

1st April 2013

My analyst series - Qualcomm (QCOM)

Another one on Qualcomm (QCOM)

Lead in mobile integrated chipset and wireless – Snapdragon series, wireless technology patents/licensing
Announced CMOS Power Amplifiers alternative to GaAs PAs for mid-high tiered 3G/4G smartphones

China market focus
- Well positioned to ride on China Mobile’s LTE wave (China Mobile announced spending $6.7b in 4G tech this year)
QCOM chips were in 14 of the 31 terminals selected for trial by China Mobile in Dec ’12 - nearest rival with 4 was Sequans.
- Biz model with local mobile chipset design companies and the system/handset manufacturers for licensing royalties

Major Revenue segments – licensing and sales
While in the last couple of years, QTL’s revenues were higher than that of QCT, QCOM is looking at double digits growth for both biz segments and QCT’s growth to be substantially higher than that of QTL.

Strong focus & investment in R&D
R&D in Q1 fiscal 2013 was 1.1B (18% of revenues)

Vertical integration for mobile eco-system
- Accelerating the commercialization of its Pixtronix MEMS displays using Sharp’s IGZO tech – Note however that the deadline for giving Sharp the 2nd half of $120m investment from QCOM has been extended now to June (due to some specs conditions not being met by Sharp)
- Ride on Internet of Things: Amongst others - Alljoyn and FlashLinq
- Moving beyond devices into wireless backhaul – DesignArt acquisition last year

Strong Financials
- Q1 ’13 earnings: $6b quarterly revenues (a 29% y-o-y increase), $1.91b profit (36% increase over previous year)
- Full-year revenue guidance to a range of $23.4 billion to $24.4 billion from its previous target of $23 billion to $24 billion.

posted in Semiconductor, Business, Fabless, 3G, Qualcomm, Ecosystem, Internet of Things, IoT, chip, connectivity, Mobile, 4G | 0 Comments

28th March 2013

My analyst series - Intel (INTC)

Going through some of the equity research notes, apart from the contents, one of the things that struck me the other day was the brief succinct way the main content is put out. And so, I thought, why not do a series with my take on some of the stakeholder companies and application markets in the semiconductor eco-system. Appreciate your feedback, comments, thanks!

So here goes the first one…

Intel (INTC)

Intel’s technology lead
- Pros: Increased capex to maintain the lead (at least 2.5 years ahead from competition), Intel’s stake in ASML for 450mm and EUV R&D
- Cons: The increased capex that could also result into high end fabs running under capacity. Intel needs to monetize its leading edge technology and also needs numbers and breadth of various types of chips to be fabricated in its fabs in order to fine tune its processes.
- As per IC Insights, Intel’s forecasted capex for period 2010-2013 is $40b, second to Samsung’s ($46.9b) – together to account for 42% of the total industry

Intel’s foundry principle seems to be - Open Intel fabs for non-Intel chips but not for competing chips (“chips for mobile biz”). Altera deal is seen as step forward. However, point to be noted is that while (reportedly) this deal does not allow Intel to let other FPGA vendors (Xilinx?) on its 14nm fabs, Altera can still continue to work with TSMC and others. Second source foundry options may not reel in 100% of Altera’s total fab requirements to Intel

Semiconductor growth drivers and Intel’s market share in it
- Slowing down/Cannibalizing of PC biz (Intel’s main revenue generator)
- Mobile chips being the major driver now for semiconductor growth and Intel’s not too effective efforts till date in this space.

• However lately, we are seeing Intel making good in-roads in this space. Mobile biz requires connectivity plus good power management solutions besides the performance factor. Two announcements from Intel this year point positively in this direction – Dialog deal (for power management in its Bay Trail (22nm)) and XMM7160 (multimode, multiband 4G LTE global modem solution) for an integrated SoC solution end 2013/early 2014.

posted in Semiconductor, Business, Technology, Intel, Ecosystem, chip, connectivity, Mobile, Power | 0 Comments

14th February 2013

Internet of Things (IoT) and the opportunities for chip biz

There has been a lot of talk on Internet of Things (IoT) or Machine2Machine (M2M) communications – which basically is an intelligent grid of devices connected to each other through the internet. Chips are embedded in the devices enabling them to relay information, take decisions, communicate commands and adjust settings/implement a requisite action(s) accordingly.

As per a report from ABI Research, over five billion wireless connectivity chips will ship in 2013.

What does this mean for the chip biz?

Some basic things that various devices involved in this IoT will include are: wireless connectivity (mostly low power unless one or more of these devices is connected to the mains), sensors, MEMs and control units.

The control units here needn’t be too fancy – efficient and sufficient enough to do the task they are assigned for. They span from low end to high end depending on the computing power required for the control functions - served by MCUs, embedded processors. The sensors (for temperature, pressure, moisture, light etc.) are coupled with accelerometers, gyroscopes and the like.

Connecting to the internet – wirelessly and power efficiently – that will be the key for connectivity stake holders in this space. Nuel has come up with an interesting way to achieve this. It recently announced a white space (unused frequencies during TV channels’ transmission) radio chip for low power communications and come out with a chip to demonstrate the same (it implements the “Weightless’ specifications)

One thing I find interesting about IoT/M2M is that it does not have any defined market space/application. There are potentially several applications, several markets where these can find their way. So, while one can chose to specialize in servicing one market/application, a choice of providing a generic chip/platform (control/sensor/connectivity) for any or combination/integration (SoC) of the components of the basic fabric for any (or at least most of the applications) is also wide open.

However, for the application to catch on, it has to be implemented in an inexpensive way and should be easy to use - and that is where we’ll see some exciting innovation & integration happening

posted in ASICs, Semiconductor, Business, Communciation, Technology, Hardware, Ecosystem, chip design, Market trend | 0 Comments

3rd July 2012

Fab Power

Looks like the scaling down road for fabless – foundry model is getting bumpier. First the high cost of setting up new fabs made the earlier IDMs get into the fab lite model – i.e. depend upon the pure play foundries for the basic process capacity and do the specialized process add-ons in-house to get the competitive advantage. The fabless companies too coupled with pure-play foundries and gained prominence. The industry seemed to have found a way out (at least temperoraliy) of the high cost challenges of scaling down coupled with the issues of designing multimillion gates chips with increasing features and decreasing time to market window.

But now the speed breakers on this road are getting frequent and higher. Take the last couple of examples. FD-SOI is one of the new transistor architectures thrown up by ST/ST-Ericsson for scaling down 28nm and below. The process is reported to give a 35% power performance gain and that too by a simpler process transition from the typical CMOS. But ST lacks the capacity and hence is exploring options with GlobalFoundries. The latter is reportedly insisting that it will use ST’s process to make parts for all other parties too, in exchange for this extra capacity – leading to ST/ST-E potentially losing on a big competitive edge of sole access to a proprietary process through its FD-SOI process.

The second recent example is of Qualcomm. The world’s largest fabless company uses TSMC‘s 28nm process to manufacture its Snapdragon S4. And the world’s largest pure play foundry has had yield/capacity issues on this node.

TSMC’s 28nm foundry capacity woes have put a dampener in the presently exclusive run of Qualcomm – the sole (at least presently) provider of integrated multimode 3G/4G LTE baseband chips. And it ripples further down the chain causing distress to LTE smartphone vendors. Shortage is not expected to cease before Q4’12. Qualcomm is now planning a 23 per cent increase in operating expenses this year and looking for alternative (apart from TSMC) suppliers. It’s CEO Paul Jacobs’s recent visit to Samsung, reportedly for discussions that included semiconductor supply as well as his comment of not ruling out owning the means of chip production has led to a lot of water cooler speculation.

Incidentally TSMC’s sales hit an all-time high (9.1% annual revenue growth) in April’12 – with much of the strong growth attributed by 28nm demand!

So where does this leave the fabless-foundry model? And how does this affect the IDMs?

One thing for sure is that the model will need to be tweaked in order to stand up to the sub 28nm/20nm challenges. Some pointers:

• Cost advantage of scaling down is diminishing for the foundries. The cost-per-transistor has been about 29% per node leading to cheaper scaled down chips. 28nm and sub has seen that levelling off for the foundries. Intel still has a big (at least a couple of years) lead in the process race. If the fabless companies do not see a steady decline in the cost-per-transistor in their foundries’ scaling, it certainly puts a spoke in their continuing down on the scaling path with this model.

• The prohibitive high cost of setting up a new fab and the related R&D and yield challenges just does not make sense for a fabless company, even Qualcomm, to start one. Owning a pre-planned and negotiated capacity or even production means with an existing foundry – yes but a fab from scratch, no, that doesn’t appear to be a viable option.

• With the increasing yield issues at smaller geometries pitched along with capacity shortage and uncertain market demand, a stronger vertical integration of supply chain may become the order of the day to sustain the fabless model – one which accounted for $64.9 billion in 2011. While expecting to resolve 28nm capacity shortage by Q4, TSMC has raised this year’s capex 42% to USD 8.5 billion to ride the market opportunities.

• Rewinding to one of my earlier blog posts (Jan 2008), I had cited a remark by Infineon’s CEO, Ziebart in an interview to EE Times’ rick Merritt, “The major thing giving semiconductor makers a competitive advantage has evaporated. Today everyone has access to the same process technology at roughly the same time. This access used to be what differentiated the best from the worst semiconductor companies, but now it has evaporated, What’s replacing process technology as a differentiator is systems know how, and it must be specific to a market area”. My comment to that, as also mentioned in the same post, was: Yes, the differentiator has moved from process technology; but it is due to access to the process techno. This access has become cost prohibitive for any single semiconductor company (perhaps leaving aside a couple with really deep pockets) and hence the scramble to find an alternate place in the value chain to survive.
That access to the process techno is now morphing, if not under threat.

• GlobalFoundties’ SVP Mojy Chian mentioned that “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market”. Now, does this mean that foundries will transition towards virtual IDMs?
Rewind to another earlier blog post (Dec 2007): “Over the last couple of years, we have seen IDMs going towards fablite and fabless models, and the emerging dominance of the original pure play foundries. I say “original” as lately these foundries are paving their way into newer territories like climbing up the design support value chain by increasing their IP portfolio, collaborating with EDA vendors for providing yield related data/information to the designers and reference design flows, and others – just short of coming up with their own ASSPs. So will we see the re-emergence of real IDMs albeit in the form of a morphed foundry??
IDMs, foundries, fabless… they are all morphing from their original identities and are reshaping the industry with their redefined (work in progress) grey and diffused boundaries

However, one thing stands tall amidst all this and that is “The “Fab power’ is increasingly getting honed into the semiconductor eco-system lately.” Fab matters

posted in Semiconductor, Process, Business, Foundry, Fabless, Technology, Samsung, Qualcomm, Intel, Ecosystem, chip design | 0 Comments

20th April 2012

Chip designing and the cloud

One way to look at how chip designing can leverage from cloud computing is to look at the main benefits of cloud computing and project the same onto IC design. Obvious ones here are on demand access to computing power and data storage in a scalable mode. It is a capex to opex biz model.


Another way of looking at is to see what are the major challenges facing an IC designer and see how cloud computing can help. I personally find the second approach as one which if addressed properly will provide much compelling reasons for the chip design community to embrace the cloud; and optimally leverage from it.


Now I would not like to open the Pandora’s Box and vent on the numerous challenges that IC designers face…it will provide enough content for a separate article! But generally speaking,  amongst the various challenges an IC design engineer faces, a vital one is Design Methodology management and that includes two vital sub issues, (a)  Accelerating Turn Around Time and (b) Verification challenges. Can the cloud address these?


Let’s look into the first one i.e. Turn-around Time. Needless to say, this is one commodity which as a customer requirement is shrinking, especially for chips in the consumer applications. And the key entity here is the efficiency and effectiveness of the design flow. A point to clarify -  by design flow here, I am referring to the common design flow framework or the chip design methodology and not about the computing power and time (which are nevertheless key and can be addressed by cloud). This includes issues like design framework, EDA tools integration and biz model, efficient and safe design data transfer across databases etc.


The biggest challenge I see in a Design Framework for cloud is the feasibility of a standardized generic flow or a common design methodology/platform. Do customers have the motivation to re-architect their existing methodologies to take full advantage of cloud? Without such a flow, cloud will provide a computing ground for multiple jobs using multiple EDA tools i.e. we would be leveraging only on the computing power and storage from the cloud.


What will provide value-addition to this power-storage combo is a seamless design flow platform for the chip designer. This may be a standardized flow or a generic one with flexibility to include changes based on user needs – a replica of what a designer does in a “cloud less’ environment.


The second challenge here is the usage of multiple point tools (both from various EDA vendors as well as the in-house tools and scripts – something which experienced designers use quite a lot). Almost no one uses a single vendor flow nowadays. Let’s say we address this by multiple clouds, each cloud serving an EDA tool from a particular EDA vendor. This will involve movement of data across clouds in order to run multiple tools on the design database at various stages –giving rise to concerns on the huge data size and its security.


A likely solution to all this may be a unified GUI framework encompassing a generic seamless design flow with multiple point tools along with an easy to integrate various tweaks in the flow. This requires collaboration across EDA vendors and therein lies the third challenge – how does one get the EDA vendors to co-operate under a unified and a commercially viable biz model. Add to it, the point that users are not likely to pay for the complete menu of a unified design flow with multiple tools from multiple vendors (or for that matter even single EDA vendors). They will pay only for the tools as and when they use them. Collaboration, Licensing and viable biz models is key.


The next issue is Verification. With verification taking almost 60-70% of the total design time and its growing importance, this has become a major contributor to sleepless nights for the IC designers. - Verification concerns include handling of humungous data and that too with a highly iterative flow, requirement of high computing power as a sustainable expense, on a need be basis, scalable (different verification tasks require different hardware) and a limitless on demand compute time, high concurrent access and synchronization of databases, data integrity (need version control) and lastly efficient handling of batch jobs as well as interactive jobs.


Apart from Design Methodology management, a couple of other stormy points in the chip design cloud path are cloud ownership and secondly the security, data integrity and back-up.

I see cloud ownership as a vital component of chip design security in the cloud. After all, if I were to place my company’s most precious assets –i.e. my chip design database – on a cloud, I will definitely like to know as to who owns the cloud. And this is on top of my regular apprehensions about my data security, back up and related aspects.


Let me clarify – I am not talking here about the infra-structure provider e.g. Amazon and the likes. Rather it is the cloud framework/database owner. The framework here includes components of the existing physical eco-system integrated together – design database, EDA tools, user interface etc. – without which cloud computing will just service individual IC design tasks i.e. storage and processing power requirements; something which on its own is not exactly fully leveraging this powerful biz paradigm shift aka cloud computing.


So the question is - who will own the chip design cloud? Will it be the foundries (also cited as “natural design aggregators”), the EDA vendors, the fabless design companies or yet another entity? The reply gleaned from most of the stormy discussions elsewhere in the nimbus zone gravitates towards foundry.


In summary, cloud computing in chip design will be a big paradigm shift and is poised to bring about tremendous benefits to the design eco-system. However for the design community to actively adopt it, the relevant stake-holders need to look into it in a holistic way and much beyond the scalable and economic computing power and data storage combo.  And this may very well redefine the existing chip design methodology.

posted in Semiconductor, Business, Ecosystem, Cloud, chio design | 0 Comments

26th January 2012

Semiconductor Ecosystem

Recently a friend shared an interesting article, “Restoring American competitiveness” by Gary Pisano and Willy Shih & printed in HBR. While the article focuses on US, it does provide a deep insight and several pointers to the local Singapore context too.

Some of the points I especially liked were the description and importance of “industrial commons “(collective capabilities)” and its role in innovation and development of the ecosystem.

It is increasingly difficult for a company to be competitive in today’s dynamic and cut-throat markets. Being competitive in today’s market requires support of an “ecosystem” of all entities involved in the supply chain like suppliers, equipment makers, customers etc.

Now can an ecosystem be defined as a mere collection or presence of all relevant entities in the same geographical space? We do have several geographies with these entities together. But what is missing – and what turns this conglomeration to an ecosystem is a proactive and broad Collaboration across the entities. And this sort of collaboration is possible only when the users have a stake in the outcome.

And this leads me to ponder – whether Singapore has the ecosystem for the semiconductor industry. And if not, then what’s missing and how do we move towards it? Suggestions??

posted in Semiconductor, Business, Ecosystem | 0 Comments

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