27th June 2006

Thermal Analysis

Thermal analysis is gaining momentum. While these analysis tools were there in the past especially with analog and mixed signal devices, they’ve lately gained prominence with sub 90nm digital designs too.

Thermal analysis tools track thermal gradients across the die. Uneven shifting of the threshold voltage, timing violations (clock timings are especially sensitive to delay variations caused by thermal gradients), leakage, electromigration, reliability are some of the thermal problems.

While some vendors are coming out with standalone thermal analysis tools e.g Gradient, some like Magma have thermal analysis in built into their power analysis tool as they believe that since power and temperature are interlinked, a user should not be shuttling between 2 separate analysis tools. As package plays a vital role in thermal analysis, some are getting package considerations also into the product.

Along with these tools, it’s the thermal management chips which are riding along the wave. According to Databeans, thermal management ICs could reach just under 2B$ in 5 years. The main growth segments cited are the ones using FPGAs and ASICs.

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9th June 2006

IC Design Houses survey by EE Times Asia (Taiwan, China)

A snapshot analysis from IC Design Houses Survey 2006 (China and Taiwan) report done by EE Times

A. Revenues
a. 2005 revenues (expected)
Average 5.4 M$ in China, 9.2 M$ in Taiwan
15 M$ and above–19 %,1-2.9 M$ - 19%,less than 250 K$ and 3-6.9M-17%
Broadly uniformly distributed
15 M$ and above – 37%, less than 250 K$ - 16%, 7-10.9 M$ and
11 – 14.9 M$ - 11%
Taiwan has extremes; 15M$ category followed by b. 2006 revenues (forecasted)
15 M$ and above – 28% (a big jump from ’05)
15 M$ and above – 53% (a big jump with a marginal increase in the lower categories)
Basically, there is a broad and uniform representation by design houses in China for all categories – small to big. This is a reflection of several design houses appearing on China’s microelectronics landscape in the last few years. Taiwan, on the other hand, being more mature in this area has most of its design houses represented in the 15M$ category and then several smaller ones.

B. Applications
- Taiwan is predominantly desktop and Laptop computers followed by
handhelds and other consumer electronics.
- China has a more even spread across handhelds/PDAs, wireless consumers,
Cellular Wireless equipment & other telecom.
- Cellular/Wireless is more than LAN/WAN equipment in China; it’s the
reverse in Taiwan.
- China also has a higher percentage in Automotives which is a growing market

C. Main difficulties when contracting foundries
China: Cycle time (54%) and cost (49%)
Taiwan: Cost (68%) and cycle time (45%)
Taiwan’s main application being Computing and Consumer Electronics which is a highly cost competitive market reflects this.

D. Design
ASICs (66%), SoC (59%), Standard IC (29%), ASSP (8%) PLD/FPGA (17%)
ASICs (61%), SoC (53%), Standard IC (28%), ASSP (19%), PLD/FPGA (7%)

- Analog/Mixed signal designs to decrease in China while there is a
slight increase in Taiwan.
- China & Taiwan – Percentage of Digital ASICs as well as DSPs to
decrease, SoC will be more or less constant.
- Taiwan has more ASSPs, an indicator of the Consumer Electronics market
with consumer focused system designs that can be rapidly configured.
- Fewer newer designs are expected in 2006 but as revenues are
expected to increase, this may indicate more revenue/design in ’06
as compared from ‘05

b. Technology/Process
Average of 10 (Taiwan) and 8 (China) design projects in ’05 with
Digital design (Taiwan/China)
0.13um (11%/ 14%), 0.18um (48%/46%), 0.25u (11%/12%), 0.35u (15%/16%), 0.5-1.5u (15%/12%)
Analog design (Taiwan/China)
0.13um (2%/10%), 0.18um (32%/24%), 0.25u (11%/15%), 0.35u (22%/16%), 0.5-1.5u (24%/25%)

- 0.18um is the most frequently used technology in both countries.
- China has more designs in 0.13um both in analog and digital as compared
to Taiwan.
- Digital designs have more or less jumped from 0.35um to 0.18um with not
many in 0.25um. Analog/Mixed Signal designs are mostly in 0.5u and
above and in 0.18um

c. Gate Count in ASIC designs
Taiwan: 3 major blocks – Less than 50K, 100k to 299k and 1 to 2.49M
China: More evenly spread. Bigger blocks are – 50k-99K, 500k to 999k,
1 to 2.49M gates

d. Challenges (Taiwan/China)
i. Reduction of design cycle time (60% / 60%)
Cycle time also figured highest for China under difficulties with foundries i.e. China’s biggest challenge is cycle time for both foundries as well as design cycle time while Taiwan has cost of foundries and design cycle time
ii. Reduction of design cost (51% / 46%)
iii. IP availability (23% / 23%)
iv. IP verification (18% / 16%)
v. DFT (5%/11%)
DFT figures higher in China. Can be attributed to higher gate complexity designs and types of designs (major applications - telecom equipment).
vi. Power Management (19% / 11%)
Power Management figures high in Taiwan after IP verification. This relates to the fact that Taiwan does a large chunk of designs for Consumer Electronics where power management is a major concern
vii. DFM (4%/ 1 %)
DFM figures higher in Taiwan. This may be attributed to the fact that the world’s top 2 foundries are from Taiwan. However, DFM is gaining momentum in sub micron technologies. So China with more designs moving to 0.13um as compared to Taiwan should have an equal if not higher figure for DFM under design challenges
viii. Design Iteration (5%/ 2%)
ix. Timing closure (5% / 2%)

E. Regional perspectives
IC design houses offer mostly Full system design followed by IP services. IP services is slightly higher in Taiwan w.r.t China (IP protection in China is a major concern and this reflected in the IP services numbers)

posted in Fabless, Survey | 0 Comments

9th June 2006

Turbulent times ahead, Gartner says

Gartner during it’s mid year update outlined 5 megatrends facing the industry - continued integration due to Moore’s Law, increasing cost and scale of manufacturing facilities, the role the consumer markets will have going forward, service providers of various kinds, and a set of new and potentially disruptive technologies.

One more major trend that I perceive, is increasing collaboration. Whether it is OEMs collaborating with service providers or EDA companies/Design houses with foundries, this collaboration will increase. This is especially true for deep sub micron technologies.

Fewer chip designs will also re-enforce EDA companies to rethink their strategies and biz models. They will need to address solutions. As pointed out by Robert Hum/Mentor Graphics, “it is time for a change”. For verification, for example, realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. An open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Technology innovations will continue, in fact grow faster. There will also be increase in the number of startups with each one of them trying to address some niche area in the market and trying to tap it in the mode they think best. However as pointed out by Gartner, the question is how many will survive the transitions.

Another outcome of fewer chip makers in the market due to increase in manufacturing scale will be the diminishing of manufacturing differentiation.

The market has moved more from standalone products to solutions. And solutions go hand in hand with service thus getting the service providers into a more prominent role. Service providers are nearer to the end customer and know their requirements which will also propel them towards a product defining role.

The growing power of the consumer market and keeping in mind its demands, will lead to more reconfigurable devices. The challenge, however, will be keeping the costs down as reconfigurability does not come with optimized silicon usage.

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6th June 2006

It’s time for a change

Yes, indeed the methodology should be done by people who know it best i.e. design engineers. EDA companies should step in to facilitate this and not formulate them. We should not have situations where the design engineer needs to grapple with firstly the design & process complexities and secondly with trying to fit the design tool into his design methodology. With the increasing complexities associated with sub micron designs, there is a need for more and more collaboration. The tasks are too mammoth and interlinked for any single entity to manage on their own. Realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. Indeed an open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

posted in EDA, Business | 0 Comments

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