26th September 2005

Freescale partners with Indian Design Houses

Comments on “Freescale partners with Indian Design Houses” by K.C Krishnadas in EE Times

This is indeed a strategy leading to multiple mutual benefits i.e. if implemented in the right spirit.

The right IP, the right technology, the optimal design flow, the right timing: neither of these factors can hold on their own in today’s volatile market. The customer wants a solution, not a set of leggo blocks left to him to assemble together.

Most of the design houses have some excellent design talent coupled with great technology, flow and ideas. But the present highly fragmented and transient market makes it very difficult for these design houses to even survive the initial few years before they hit the market and revenues start trickling in. The ruthless market conditions have led to the premature demise of many a promising design houses. With the multinationals tapping on these entities for domain know how and a basic solution using their IPs and the design houses leveraging on the multinationals’ clout (financial and market channels), it can be a win-win situation.

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19th September 2005

Open-Silicon automates the flow

Refering to When infrastructure is essence: Open-Silicon automates the flow , an article posted in Electronic Engineering Times by Ron Wilson on Sep 16 2005

ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.

Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.

It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.

Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.

posted in ASICs, EDA | 0 Comments

16th September 2005

Taiwan as centre of IC world

Comments on “Seeing Taiwan as centre of IC world”, an interview of Nicky Lu by Mike Clendinin

IPs fill up the differentiating edge gap in a product leading to higher sales and thus higher revenues. But the broad definition of IP has also changed over the years. What was initially termed as the “winning” block in a chip has now become a generic part. So one needs to keep up innovating to come up with new IPs, new value-addition to the IC.

In the “manufacturing reigns supreme” years, Taiwan had the edge of having the wafer fab, assembly & testing plants as well as multiple design houses in the vicinity. Later when this along with the lower cost was no longer sufficient, foundries started focusing more on their IP portfolios and now on addressing the various issues arising in the design chain, in addition to the manufacturing issues. This has also been a triggered by the need of the “falling of the walls” between the design space and manufacturing space. Forced or not, this is good for the industry especially in the DSM zone.

Given the earlier edge of having in place the basic semiconductor ecosystem, Taiwan can be strongly poised if it can efficiently harness the synergy from it as an integral unit rather than as separate entities.

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1st September 2005

Leaky chips test designers’ skills

Refering to Leaky chips test designers’ skills by Mike Clendinin in www.eetasia.com

Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.

And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.

posted in EDA | 0 Comments

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