1st September 2005

Leaky chips test designers’ skills

posted in EDA |

Refering to Leaky chips test designers’ skills by Mike Clendinin in www.eetasia.com

Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.

And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.

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