Travelling On The Silicon Road

Cadence is slated to release its Low Power Methodology Kit in late June. The highlight of the kit is a wireless “representative design” implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design has sample IP including a processor and bus fabric from ARM, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm low-power memories from Virage Logic and 65nm technology libraries from TSMC.

While till date, EDA vendors have been mostly dishing out different point tools to address the industry’s power concerns, a big challenge is to help designers utilize the appropriate low power techniques and tools effectively and seamlessly within their flow on a real design – and in a timely manner. They need to be aware of the trade-offs required and some balancing tips to make the exercise productive.

A representative design is a step forward in this direction. The objective may be to regain the lead in the format war, but if it helps the end user, it definitely signals well!

Synplicity rolled out its Synplify DSP ASIC Edition software at the Design Automation and Test Europe conference in France. Their earlier ESL synthesis tool was aimed at FPGA designs. With this new offering, they are targeting customers who use FPGA prototyping for their DSP based ASICs.

Another recent news has been that TSMC is broadening its IP portfolio giving worries to IP providers and speculation in the industry whether TSMC is moving towards ASIC like biz model.

Gives a new meaning to the phrase “ASIC demise”………

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing noted in his presentation at the SPIE Advanced Lithography Conference last week that while there are some good point tools for DFM, integrated DFM solutions are still lacking.

As I noted in an earlier post, Why can’t we do it in EDA?, it is a huge task for a single vendor to handle even most of the important sources of variations through a single integrated flow. Integration of point tools requires standardization as well as agreement over interfaces and formats.

IBM’s Leon Stok had identified 4 eras in the EDA industry. For the 4th era i.e. design implementation platforms, he mentioned that we would need to define standards as APIs in order to allow tools to talk to each other.

The trend is moving more and more towards a hybrid approach

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –

1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
2. Tradeoff analysis that lets users adjust specifications to impact yield
3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

With verification consuming up to 70% of design effort and debug up to 50% of that time (this means up to 35% of overall design time is spent understanding how a design works or why it doesn’t!) - I share Richard Goering’s musing that it’s a wonder that EDA vendors have paid little attention to post-silicon debug.

Post-silicon validation being a confrontational sale may be a significant hurdle for selling wares in this space. However another not so insignificant fact is that post-silicon validation is done in 2-3 phases – first on standalone chip, then on the system and then the field trials. The latter two being heavily dependant on applications and the working environment pose too many variables in the debug process and it is not an easy task to implement all these in a tool. Nevertheless it is a fact that good solutions in this space will be a boon to the chip designer (not to say the S&M guys who keep their fingers crossed while awaiting reports of field tests and subsequently news on the 1^st order…)

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, “Wherever the industry takes CPF and UPF, if the users want it, we’ll do it. If you’re a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it’s CPF or UPF or some common thing in the future doesn’t matter any more. We’ve got the software system that will build the chips, and we’ll follow wherever the standard goes.”  

Let’s see what follows from the rival potential standard’s camp……

Cadence’s primary EDA rivals felt that Power Forward Initiative introduced by Cadence in May ’06 wasn’t open and inclusive and joined another coalition – Accellera UPF effort in Sep. Si2’s Low Power Committee (LPC) was set up in Oct as an attempt to bridge the gap and address users’ requirement of having a single low power specification format.

Si2 first approved CPF 1.0 saying that its approval of CPF 1.0 does not constitute taking sides and that they have declared it as a “specification” and not a “standard”. This may be a conciliatory offer to Accellera which said that they are actively working with Si2 to converge UPF and CPF into a single standard. Then Si2 issued a RFT to complement the CPF and Cadence in its response has now provided them the source code of its CPF 1.0 parser; in the process opening the door to tool implementation that supports CPF ……. and hence giving another push to boost their format

A boost to SSTA…..Altos has introduced Variety, a SSTA library characterization tool. While there do exist similar tools in the market, Altos’ niche factor is that it supports multiple formats (unlike Cadence, Synopsys, IBM, Magma etc. which support only their proprietary formats). This is definitely an advantage as it gives flexibility to the user to switch across various flows/vendors.

Characterization speed and accuracy, the two most important aspects in library characterization, are something which Altos promises through this tool.

Yet another DFM tool in the market.

DFM Blaze announced a DFM tool, Blaze IF, to address topology variations caused due to CMP. It intelligently inserts dummy metal fill patterns into a design layout taking into account not only the design requirements like power and timing needs, but also the electrical issues like signal integrity and IR drop – which traditional approaches to metal fill do not accomplish.

This is in addition to the announcement of Blaze MO, announced earlier this year which provides guidance to OPC tool used in manufacturing through an annotation layer in the GDSII database. The tool optimizes the design by small tweaking of the gate lengths (within the process limits) for reducing leakage power and improving timings and provides this guidance to the OPC tool.

All these aim to bridge the gap between design and manufacturing. Instead of a blanket set of rules for the complete design, design specific and design objectives’ relevant optimizations are carried forward to the manufacturing. Making it an integral part of the flow before handoff to manufacturing is a step closer to address issues arising out of the open loop caused by changes made to the design after handoff – oblivious to the design issues which may be impacted.

An interesting take on the EDA industry evolution and look into the trend by Leon Stok, director of EDA for IBM’s Systems and Technology Group in a keynote address at the International Conference on Computer Aided Design (ICCAD).

Stok identified three previous innovation eras in the EDA industry — those of invention, implementation, and integration. The fourth era, he said, is the one we’re about to enter and is centered on design implementation “platforms”. To make platform innovation happen, Stok said, we will need to define standards as APIs, not ASCII formats. This will allow tools to talk to each other, instead of producing data that another tool can barely read, he noted.

With APIs, smaller companies with innovative potential solutions for the UDSM technology challenges will have a more level playing field. Each can plug in their solutions and then let the market forces decide. It will also pave the way for the bigger players as they too can focus on the overall user flow with a market decided mix of their own in-house tools or point tools from other companies.

The organizers of ICCAD (International Conference on Computer Aided Design) decided to do something different and added a designer’s perspective track this year.

“Our goal is to bridge the gap between practitioners and research,” said ICCAD general chair Soha Hassoun, an associate professor of electrical engineering and computer science at Tufts University (Medford, Mass.), in opening remarks at the conference. “We would like them [designers] to tell you [researchers] what critical issues should drive CAD research in the next few years.”

Now, I would term this as going back to basics. The users tell their requirements to the researchers which in turn guides the researchers towards the right direction in terms of practical benefits and usage of their efforts – optimal Lab to Fab transition.

Another tenet emphasized was by STMicroelectronics’ Pascal Urard: “We need academia and the EDA community to think at the flow level, not only at the tool level”.

It is apt to remind the EDA community that they should enable the end user with his final flow and not only the point tools. It’s true that tools provide the differentiating edge amongst the EDA vendors and users should have the flexibility of picking up the ones which best suit his flow.

However, to justify the “Automation” in “EDA”, it pays to facilitate the flow.

This was the questioned posed by Chairman of Orb Networks and former CEO of Cadence, Joe Costello in his DAC 2006 keynote speech.

The “it” referred to here is the mix and match of new plug-ins (internal and external), bundling things on top of others’ offerings and selling directly to customers.

With the increasing complexity of technological challenges compounded by rising market pressures, it does indeed benefit both the big EDA companies as well as the small start-ups with niche solutions to collaborate. However, opening the tools and making them pluggable is not without its major share of teething issues. While standards do take a long time to be formulated and then adopted, they’ll still be required to an extent for “universal plug-ins”.

One scenario is where EDA companies have the basic engines for the standard design activities. To these, smaller niche companies provide their plug-ins for value-addition and tackling of issues related to leading edge designs. With a uniform standard, these companies can go with their plug-ins to various EDA companies. In its absence however, each EDA company will need to work closely with these smaller companies and sell the complete “bundle with options” to the user.

A point to be noted here is that it’ll be naïve to assume that the present basic engines are implemented in a modular fashion where a plug-in can be used in a quasi seamless fashion. Then comes the question: if addressing of the leading edge issues is done in a modular fashion by the smaller companies who are free to sell their wares to the other big EDA companies, what is in it for the big EDA companies? What will be their competitive edge? But on the flip side, if the major EDA companies persist in attempting to do everything on their own, given the complexities and constraints, it’ll not result in much growth for the EDA industry.

Interestingly, there are signs of the industry moving in this direction. For DFM, with TSMC sharing their process information with the EDA companies to integrate into their design flow is one example. This can be treated as a “plug-in”.

Let’s take an example here: Synopsys recently came out with 3 tools in the DFM space - LCC (lithography compliance checking), CMP (chemical-mechanical polish) checking, and CAA (critical-area analysis). As per the press note, LCC inspects GDS-II files using a rapid-computation model of the lithography process, calibrated with foundry data. This scan predicts the actual shapes the mask features will produce, across the focus window of the lithography step. It then examines these features against a rule set to detect pinch-off, end-shortening, bridge, and other faults that could occur with a reasonable probability.

The normal output of the device is a color-coded die map: green for areas that pass, yellow for areas of concern, and red for trouble spots. Design teams that are knowingly pushing the litho rules can look under this graphic presentation at a numerical database that will give them actual predictions of critical dimensions.

Designers can then invoke an auto-correction tool, which is based on extensive, process-dependent heuristics, to deal automatically with the majority of the problems—adding space between lines, moving edges or corners, and other such reasonable measures.

Now reconsider the situation with a small EDA company working on the basic LCC part. It takes inputs from the lithography process model provided to it by the big EDA vendor (I don’t think the big foundries will be that comfortable in working closely with the smaller companies in handling their process data!). The GDSII is also provided as an input from the big EDA vendor’s tool(s). Finally the auto correction tool can be provided by either.

I cite this example because while these three new tools do attempt to handle the first order problems, they do not even begin to cover all the important sources of variation in 90-nm and finer geometries. TSMC cites more than 2000 independent sources of potential trouble.

I see a hybrid approach in the near future………

TSMC had recently unveiled its 65nm DFM compliance design support ecosystem by coming out with its DFM Data kit compiled with DFM Unified Format (DUF). DUF has been developed by TSMC to align DFM tools. This kit would help to put the fabless designers on an equal footing with the IDMs. The format, though, models only random and systematic defects with parametric defects being planned for a future release.

Now yet another tool has hit the “in news” DFM space.

Blaze DFM Inc recently rolled out its solution Blaze MO. It is marketed as targeting to improve the parametric yield through a better control over leakage, timing and variability.
It has an electrical focus in contrast with other DFM tools which have a geometric focus (focusing on wire spreading, lithography simulation and critical area analysis)

The heat is on…….