Archive for December, 2007

SoC yield management – an emerging issue that could reshape the industry?

Wednesday, December 26th, 2007

Read this interesting commentary by EDN’s Ron Wilson on Verigy’s acquisition of Inovys. While relating the ATE vendor’s acquisition as more towards acquiring Inovys’ failure localizing software, Ron has brought about an interesting emerging industry aspect

With “Time to entitled yield” becoming a critical metric especially for 65nm and below, it is doubtful if the existing distributed manufacturing model used between fabless companies and their foundry partners will suffice.  A closer loop is required which will cross the existing collaboration and contractual working relationships.And this leads to Ron’s observation – will we gradually see re-integration of design, test and failure analysis functions into real IDMs? 

Over the last couple of years, we have seen IDMs going towards fablite and fabless models, and the emerging dominance of the original pure play foundries. I say “original” as lately these foundries are paving their way into newer territories like climbing up the design support value chain by increasing their IP portfolio, collaborating with EDA vendors for providing yield related data/information to the designers and reference design flows,  and others – just short of coming up with their own ASSPs. 

So will we see the re-emergence of real IDMs albeit in the form of a morphed foundry??

Fab lite diet for analogs?

Thursday, December 6th, 2007

Over the last few years, we have been seeing IDMs outsourcing their digital production needs to the foundries. Now looks like, a similar path may be taken by the big analog IDMs too – or at least “their interest level in outsourcing has dramatically increased”, as per Thomas Hartung, VP of Sales & marketing for X-Fab.

Read a couple of interesting articles which highlight this potential move; here are few points from them which I’d like to share:

For years, analog IDMs have manufactured the bulk of their products in-house, shipping only a small percentage to foundries, for a number of reasons.

-    Many analog products do not require leading-edge fabs or processes. -    Most analog ICs have relatively small die sizes and wafer volumes are hence low as compared to their digital counterparts ; this does not work well with outside foundries-    Analog products generally have longer life cycles and can be made cheaply in older fabs for several years.

-    The real money makers in analog sell in modest volumes year after year; something that works for an internal fab but not at an expensive foundry.

-    And analog vendors insist fabs still give them a competitive edge as they work on the edges of highly optimized, internally developed processes

This doesn’t mean foundries have no role in the analog IC world. Foundries can effectively support fabless vendors of ICs that have considerable digital content but only modest analog content and that don’t push the envelope of analog performance. On the other hand, the specialized foundries are trying to get these analog IDMs look more towards outsourcing their production needs to them. Hans-Jurgen Straub, CEO, X-Fab Group, says that analog IDMs should focus on product innovation rather than on process innovation. Besides pushing its own analog & mixed signal processes, Germany’s X-Fab has also been acquiring fabs from various IDMs.(a US fab from TI in 1999, a UK fab from Zarlink semiconductor in 2002,  last year acquisition of Malaysia’s 1st Silicon and then ZMD AG’s wafer processing subsidiary early this year).

So, it is to be seen whether the analog IDMs will beat the same path as digital IDMs or continue in the old fashioned way  

Decline in ASIC design starts

Wednesday, December 5th, 2007

The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4 percent from 2006’s 3,408, according to market research company Gartner Inc. Of the 2007 ASIC design starts, about 200 starts made at 65-nanometer design rules or below.

A few interesting points from this report:

- In general ASIC design starts are declining. Exponentially increasing cost at leading edge plus a strong ASSP offering (which amortizes costs across multiple customers) are cited as the main factors. - Companies pushing leading-edge ASIC designs tend to be in high-performance computing, wired communications, high-end storage, high-end cellular phones and video game consoles.

- The average revenue per design and the average units per design continue to rise, resulting in overall growth in ASIC revenue.

- Designers in China are not using leading edge technologies; hence contribute to slowing of the overall ASIC start-ups’ decline.

- This also leads to China representing a market with ASIC growth potential.

- More ASIC design starts are predicted in Asia-Pac

Now, we have been talking of ASIC decline for the last 5-6 years. The question remains: is there any life left in the ASIC market? The answer is a provisional “yes.” as per  Hugh Durdan, vice president of marketing for eSilicon Corp, a fabless ASIC house and I am inclined to agree with him due to the following reasons:

- Inspite of overall decline in ASIC design starts, overall revenue is increasing. Big players like Cisco, Nortel and other major OEMs continue to use ASICs for differentiation

- While FPGAs have improved in their race to catch up (and substitute) ASICs, the gap still remains. Structured ASICs have tried to fill this gap but have had a mixed response from the industry and market. Till the industry figures out a way to address this gap, ASICs and FPGAs will co-exist

- The big ASIC players have come up with various approaches to revive this ASIC market. Some of them are:

- IBM, world’s no 2 ASIC supplier (after TI) maintains that they do not see any slow down. It rolled out its ASIC offering this year in 45nm techno which combines embedded DRAM with SOI technology. However, let me add that this is more geared towards niche & bleeding edge applications and the mainstream ASIC sector consists of products based on 130- and 90-nm technologies and the 65-nm ASIC market remains small. Also SOI is more costly than the traditional bulk silicon process and this may not help the mainstream ASIC market.

- Earlier this year, NEC Electronics rolled out the CB-55L, a cell-based ASIC technology built around a 55-nm process. Believed to be the world’s first logic device that utilizes a high-k dielectric film for the gate stack, it claims to reduce leakage current and improve power consumption by 40 percent over previous 90-nm devices

- Toshiba is readying its previously announced, 45-nm ASIC line. The technology is based on bulk CMOS, which it claims will outperform the SOI-based offering from IBM.