Travelling On The Silicon Road

Qualcomm, with its IFM (Integrated Fabless Manufacturing) strategy is quietly but steadily decreasing the gap between itself and IDMs in new process adoption time. The world’s largest fabless design company is leading the way in how the fabless design community needs to overcome the DSM hurdles of the widening gaps between IC design and manufacturing flows.

While not exactly striving to be process experts, Qualcomm has formed a virtual manufacturing organization including its VLSI Technology organization and DFX unit which has helped it to understand, appreciate and thus resolve a host of complex and costly issues. The results, closing of the technology gap with the IDMs, are the proof.
They are cautious enough, though, as to not necessarily be the first ones to ship out a new product on a new technology node.

With Paul Jacobs’ strategy of making people understand that Qualcomm is a wireless technology company and not just a CDMA company, it needs all the efforts and results to zoom to the next node in a competitive manner.

Atheros recently picked up Attansic Technology, a designer of Ethernet chips in Taiwan for its Gigabit Ethernet technology for 802.11n market. Attansic is a subsidiary of Asustek. Craig Barratt, CEO of Atheros said, “there has really been tremendous growth in companies in Taiwan doing pretty impressive R&D, creative engineering and product development.”

Moving to India – India needs to include IPs and technology know-how into their growing expertise portfolio. As I mentioned in an earlier post, product know-how is essential for the differentiating factor. With its relatively better copyright rules as compared to China for example, if the Indian companies can supplement their design skills and embedded software expertise with the product & technology know-how, they can raise the stakes higher.

There are some examples like Wipro, Tejas Networks etc. but it’ll be good to see this list grow.

A snapshot analysis from IC Design Houses Survey 2006 (China and Taiwan) report done by EE Times

A. Revenues
a. 2005 revenues (expected)
Average 5.4 M$ in China, 9.2 M$ in Taiwan
China
15 M$ and above–19 %,1-2.9 M$ - 19%,less than 250 K$ and 3-6.9M-17%
Broadly uniformly distributed
Taiwan
15 M$ and above – 37%, less than 250 K$ - 16%, 7-10.9 M$ and
11 – 14.9 M$ - 11%
Taiwan has extremes; 15M$ category followed by b. 2006 revenues (forecasted)
China
15 M$ and above – 28% (a big jump from ’05)
Taiwan
15 M$ and above – 53% (a big jump with a marginal increase in the lower categories)
Basically, there is a broad and uniform representation by design houses in China for all categories – small to big. This is a reflection of several design houses appearing on China’s microelectronics landscape in the last few years. Taiwan, on the other hand, being more mature in this area has most of its design houses represented in the 15M$ category and then several smaller ones.

B. Applications
- Taiwan is predominantly desktop and Laptop computers followed by
handhelds and other consumer electronics.
- China has a more even spread across handhelds/PDAs, wireless consumers,
Cellular Wireless equipment & other telecom.
- Cellular/Wireless is more than LAN/WAN equipment in China; it’s the
reverse in Taiwan.
- China also has a higher percentage in Automotives which is a growing market
there.

C. Main difficulties when contracting foundries
China: Cycle time (54%) and cost (49%)
Taiwan: Cost (68%) and cycle time (45%)
Taiwan’s main application being Computing and Consumer Electronics which is a highly cost competitive market reflects this.

D. Design
a. Types
China
ASICs (66%), SoC (59%), Standard IC (29%), ASSP (8%) PLD/FPGA (17%)
Taiwan
ASICs (61%), SoC (53%), Standard IC (28%), ASSP (19%), PLD/FPGA (7%)

- Analog/Mixed signal designs to decrease in China while there is a
slight increase in Taiwan.
- China & Taiwan – Percentage of Digital ASICs as well as DSPs to
decrease, SoC will be more or less constant.
- Taiwan has more ASSPs, an indicator of the Consumer Electronics market
with consumer focused system designs that can be rapidly configured.
- Fewer newer designs are expected in 2006 but as revenues are
expected to increase, this may indicate more revenue/design in ’06
as compared from ‘05

b. Technology/Process
Average of 10 (Taiwan) and 8 (China) design projects in ’05 with
Digital design (Taiwan/China)
0.13um (11%/ 14%), 0.18um (48%/46%), 0.25u (11%/12%), 0.35u (15%/16%), 0.5-1.5u (15%/12%)
Analog design (Taiwan/China)
0.13um (2%/10%), 0.18um (32%/24%), 0.25u (11%/15%), 0.35u (22%/16%), 0.5-1.5u (24%/25%)

- 0.18um is the most frequently used technology in both countries.
- China has more designs in 0.13um both in analog and digital as compared
to Taiwan.
- Digital designs have more or less jumped from 0.35um to 0.18um with not
many in 0.25um. Analog/Mixed Signal designs are mostly in 0.5u and
above and in 0.18um

c. Gate Count in ASIC designs
Taiwan: 3 major blocks – Less than 50K, 100k to 299k and 1 to 2.49M
gates
China: More evenly spread. Bigger blocks are – 50k-99K, 500k to 999k,
1 to 2.49M gates

d. Challenges (Taiwan/China)
i. Reduction of design cycle time (60% / 60%)
Cycle time also figured highest for China under difficulties with foundries i.e. China’s biggest challenge is cycle time for both foundries as well as design cycle time while Taiwan has cost of foundries and design cycle time
ii. Reduction of design cost (51% / 46%)
iii. IP availability (23% / 23%)
iv. IP verification (18% / 16%)
v. DFT (5%/11%)
DFT figures higher in China. Can be attributed to higher gate complexity designs and types of designs (major applications - telecom equipment).
vi. Power Management (19% / 11%)
Power Management figures high in Taiwan after IP verification. This relates to the fact that Taiwan does a large chunk of designs for Consumer Electronics where power management is a major concern
vii. DFM (4%/ 1 %)
DFM figures higher in Taiwan. This may be attributed to the fact that the world’s top 2 foundries are from Taiwan. However, DFM is gaining momentum in sub micron technologies. So China with more designs moving to 0.13um as compared to Taiwan should have an equal if not higher figure for DFM under design challenges
viii. Design Iteration (5%/ 2%)
ix. Timing closure (5% / 2%)

E. Regional perspectives
IC design houses offer mostly Full system design followed by IP services. IP services is slightly higher in Taiwan w.r.t China (IP protection in China is a major concern and this reflected in the IP services numbers)

I recently read the latest report from EE Times and Gartner Dataquest on Design Trends & EDA Tools : China & Taiwan. It can be accessed from their website http://www.eetasia.com.

The report makes a very interesting reading and made me ponder on a few points…….

ASIC Design segment

A. Application segment
While consumer applications remained the major application segment in Taiwan (as was in ’04 too), it displaced Telecom/Datacom in China to be the major one there too. Some possible underlying reasons (apart from generic market conditions) could be
· Telecom/Datacom designs have traditionally been using the leading edge process geometry. The rising mask costs associated with them could have been a factor of the decrease in new ASIC designs.
· The varied & vast set of categories within the consumer applications mkt. abets more ASIC designs and spin-offs.
· More consumer ASICs are coming out with the rapid growth of the China consumer mkt.

B. Gate Count
The general increase in the gate count follows the rising complexity which is also aided by the integration of various functions/categories in a single product.
Majority of the respondents working on large designs are companies that are local subsidiaries of foreign companies or local ventures – not joint ventures with foreign companies. This is mostly due to the high costs involved in large & complex designs. It makes sense for joint ventures with foreign companies to focus on the local marketing & enhance their foreign partner’s footprint in the local mkt.

C. Process Geometry
China figures indicate a more rapid embracing of newer technos.
The 0.18um in Taiwan, apart from remaining the predominant node for the past 3 years, has grown from 35% from last year to 44% while the 0.13um has increased from 13% to 23%.
0.18um is still the dominant node in China. However, it’s share has slightly decreased from 49% to 45%. But it’s in the 0.13um that we see the real increase – 12% to 31%

D. IP core usage rate
EDA companies’ share has decreased and has been correctly attributed to their partnering with foundries. With the increasing complexities and the focus going more towards Design for Yield, it is natural for foundries to play a major role in this partnership with EDA vendors/3rd party IP suppliers. The growing complexity of selecting the right IP & the subsequent issues seen during their integration in the design compel companies resort to developing them in-house. The marked surge in the independent 3rd party suppliers is also due the fact that they specialize in their niche IPs & these IPs are their main products.

EDA tools usage
Increasing reliability and reduced costs are the paramount factors for the electronic designers in Taiwan (increased functionality is no longer the most important goal) while increased functionality and reduced cost are the most important goals for the designers in China.

This possibly indicates a more mature market (in terms of EDA tools usage) in Taiwan where they seem to be more conversant and satisfied with the various functionality features offered by the EDA tools and hence are focusing more on reliability i.e. fewer issues while going through the design flow and hence shortening their time to market.
Cost reduction remains common; not surprising where Consumer applications is the predominant market.