Travelling On The Silicon Road

In the interview to EETimes’ Rick Merritt, Infineon’s CEO, Ziebart mentioned that semiconductor companies need to shift their focus from building fabs to building systems, and they must engage with customers at deep technical levels if they are to survive the current wave of consolidation.

“The major thing giving semiconductor makers a competitive advantage has evaporated. Today everyone has access to the same process technology at roughly the same time. This access used to be what differentiated the best from the worst semiconductor companies, but now it has evaporated, What’s replacing process technology as a differentiator is systems know how, and it must be specific to a market area”, he said.

This has initiated several comments on the blogosphere. Let me add my two penny’ worth to that:

In the past, the process technology was the competitive edge. Later the escalating costs (& risks) involved with building new fabs & developing new processes left one with little option but to pool in resources and consolidate (to compete with the rising prominence of  original pure-play foundries); giving rise to alliance like Crolles and later the Common Platform Alliance. IDMs shared their resources for the basic process and individually derived some spin-offs for differentiation & niche. This competitive edge was further complemented and later more or less replaced with strong IP portfolio which has grown over the years from a block to platform to “platform plus services”.

Moving to system level is a natural progression in this path.

Yes, the differentiator has moved from process technology; but it is due to access to the process techno. This access has become cost prohibitive for any single semiconductor company (perhaps leaving aside a couple with really deep pockets) and hence the scramble to find an alternate place in the value chain to survive.

A point to be noted here is to follow how the foundries have also evolved over this period –  from pure play to design support to building an IP portfolio to……. “systems know how”???

ISNE (Institute for Sustainable Nanoelectronics) is a new initiative established by Nanyang Technological University (NTU) and aims at developing next-generation embedded IC chips that consume over 100 times less energy, as well as cut design and production costs.

ISNE aims to evolve a platform independent design methodology that can exploit the exponential rate at which the size of electronic component has been shrinking, while tying the costs for design, energy consumption and production. ISNE will receive a seed funding of $2.618 million from NTU over two years and the institute will collaborate closely with Rice University’s Value of Information-based Sustainable Embedded Nanocomputing Center (VISEN), which was founded and directed by Krishna Palem, an NTU visiting professor from Rice university and who has invented probabilistic CMOS (PCMOS). The PCMOS approach is claimed to allow chips to use less energy and attain nano-dimensions, enabling longer battery life and faster turn-around in new designs. The research team is currently designing and building the first production prototype of these new ICs.

What brings this news closer is that a key member of this initiative is Prof. Yeo Kiat Seng, an EE professor at NTU and also a member of MIDAS’ executive committee.

IBM and its Common Platform agreement partners will extend their development relationship to 32nm too.

The group started with 2 partners – IBM and Chartered. This later included Infineon, Samsung, and now Freescale. In addition, with the collapse of Crolles Alliance, it can also draw more partners.

While collaboration is a necessity in these process nodes and the Common Platform Agreement has been doing quite well, there have been reports (which subsequently have been dismissed as rumours) that the foundry vendors in the alliance are struggling with compatibility issues - and this can get compounded with increasing number of members.

So, a foundry has closed the gap with an IDM!

In all likelihoods, TSMC will be in volume production for 45nm at the same time as Intel – in first half of 2008. As noted by David Manners in an an earlier post, “With all this third party expertise soaking up the industry’s value-add, where is there to go for the IDMs?”

Renesas seems to be bucking the trend of IDMs relying more and more on foundries for advanced process technology development.

Renesas believes in working (on its own or in collaboration) on advanced process development. With plans to increase sales in system-on-chip solutions and microcontrollers, it may make sense to keep the advanced process development in-house in order to have more control and direction for their major product offerings.

This, however, will not prevent it from outsourcing for volume production on advanced devices

Mark LaPedus reports in his article in EETimes about TI’s approach towards IC manufacturing – while bolstering its in-house effort in analog production, TI is shifting more of its logic based work & process flow to foundries.

TI is adopting a 3 pronged approach based on its product categories - At the 65-nm node, TI has three foundry partners for its wireless chips: Chartered, TSMC and UMC. For wireless chips at 45 nm, TI will continue to use UMC and TSMC. For DSPs, TI develops the processes & makes its own 65nm DSP. However it will rope in TSMC too for the next node. TI has been manufacturing Sparc processors for Sun; a foundry, probably UMC, will take over production at 45nm.

Shifting the responsibility of digital processes to outside foundries, while focusing on analog processes for in-house manufacturing does seem to be the right direction, especially now when the production costs & risks are escalating. However, this is not an all together new approach. If I recollect well, STMicroelectronics had followed this approach along with TSMC. While the base/digital process was same across the two companies, STM developed its own spin-offs e.g. analog, high power, RF for and based on its market requirements.
The advantages are: risk sharing (in certain cases, offloading) in base process, retaining its niche in customized or spin-off processes and having the second source options when capacity is needed.

The article mentions that by using leading-edge foundries, fabless Qualcomm Inc. has been able to close the manufacturing gap with rival TI. I would say that it wasn’t just using leading edge foundries; it was close co-operation with multiple leading edge foundries coupled with the adoption of what it termed as Integrated Fabless Manufacturing Strategy (IFM) that helped Qualcomm. As I noted in my earlier post, “Fabless Qualcomm zooms to next node“, (incidentally a comment on another article by the same author!) Qualcomm developed its own virtual manufacturing organization.

Intel is hogging the silicon limelight with it’s news on the technology breakthrough - usage of high-k and metal gate transistors for 45nm technology.

Scaling without losing out much on leakage is the driving advantage. The major advantage, though, is that with this technique, Intel will not have to significantly change its current production process. This is different from the alternative solution being disclosed by IBM and its partners. The latter involves SOI which is a more expensive production technique and they plan to later switch to immersion lithography. Another lead for Intel is that the production with this new technique starts mid this year whereas IBM plans production in end 2008.

Having said that, it still appears that while Intel has stolen the lead in announcing the breakthrough with earlier production planned (and that too across servers, desktops and laptop applications), IBM will have a long term advantage as its technology involves integration of the metal gates so that they are embedded in silicon as compared to Intel where they sit atop a proven silicon architecture – thus solving long range problems and more future transitions.

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..