20th April 2012

Chip designing and the cloud

One way to look at how chip designing can leverage from cloud computing is to look at the main benefits of cloud computing and project the same onto IC design. Obvious ones here are on demand access to computing power and data storage in a scalable mode. It is a capex to opex biz model.


Another way of looking at is to see what are the major challenges facing an IC designer and see how cloud computing can help. I personally find the second approach as one which if addressed properly will provide much compelling reasons for the chip design community to embrace the cloud; and optimally leverage from it.


Now I would not like to open the Pandora’s Box and vent on the numerous challenges that IC designers face…it will provide enough content for a separate article! But generally speaking,  amongst the various challenges an IC design engineer faces, a vital one is Design Methodology management and that includes two vital sub issues, (a)  Accelerating Turn Around Time and (b) Verification challenges. Can the cloud address these?


Let’s look into the first one i.e. Turn-around Time. Needless to say, this is one commodity which as a customer requirement is shrinking, especially for chips in the consumer applications. And the key entity here is the efficiency and effectiveness of the design flow. A point to clarify -  by design flow here, I am referring to the common design flow framework or the chip design methodology and not about the computing power and time (which are nevertheless key and can be addressed by cloud). This includes issues like design framework, EDA tools integration and biz model, efficient and safe design data transfer across databases etc.


The biggest challenge I see in a Design Framework for cloud is the feasibility of a standardized generic flow or a common design methodology/platform. Do customers have the motivation to re-architect their existing methodologies to take full advantage of cloud? Without such a flow, cloud will provide a computing ground for multiple jobs using multiple EDA tools i.e. we would be leveraging only on the computing power and storage from the cloud.


What will provide value-addition to this power-storage combo is a seamless design flow platform for the chip designer. This may be a standardized flow or a generic one with flexibility to include changes based on user needs – a replica of what a designer does in a “cloud less’ environment.


The second challenge here is the usage of multiple point tools (both from various EDA vendors as well as the in-house tools and scripts – something which experienced designers use quite a lot). Almost no one uses a single vendor flow nowadays. Let’s say we address this by multiple clouds, each cloud serving an EDA tool from a particular EDA vendor. This will involve movement of data across clouds in order to run multiple tools on the design database at various stages –giving rise to concerns on the huge data size and its security.


A likely solution to all this may be a unified GUI framework encompassing a generic seamless design flow with multiple point tools along with an easy to integrate various tweaks in the flow. This requires collaboration across EDA vendors and therein lies the third challenge – how does one get the EDA vendors to co-operate under a unified and a commercially viable biz model. Add to it, the point that users are not likely to pay for the complete menu of a unified design flow with multiple tools from multiple vendors (or for that matter even single EDA vendors). They will pay only for the tools as and when they use them. Collaboration, Licensing and viable biz models is key.


The next issue is Verification. With verification taking almost 60-70% of the total design time and its growing importance, this has become a major contributor to sleepless nights for the IC designers. - Verification concerns include handling of humungous data and that too with a highly iterative flow, requirement of high computing power as a sustainable expense, on a need be basis, scalable (different verification tasks require different hardware) and a limitless on demand compute time, high concurrent access and synchronization of databases, data integrity (need version control) and lastly efficient handling of batch jobs as well as interactive jobs.


Apart from Design Methodology management, a couple of other stormy points in the chip design cloud path are cloud ownership and secondly the security, data integrity and back-up.

I see cloud ownership as a vital component of chip design security in the cloud. After all, if I were to place my company’s most precious assets –i.e. my chip design database – on a cloud, I will definitely like to know as to who owns the cloud. And this is on top of my regular apprehensions about my data security, back up and related aspects.


Let me clarify – I am not talking here about the infra-structure provider e.g. Amazon and the likes. Rather it is the cloud framework/database owner. The framework here includes components of the existing physical eco-system integrated together – design database, EDA tools, user interface etc. – without which cloud computing will just service individual IC design tasks i.e. storage and processing power requirements; something which on its own is not exactly fully leveraging this powerful biz paradigm shift aka cloud computing.


So the question is - who will own the chip design cloud? Will it be the foundries (also cited as “natural design aggregators”), the EDA vendors, the fabless design companies or yet another entity? The reply gleaned from most of the stormy discussions elsewhere in the nimbus zone gravitates towards foundry.


In summary, cloud computing in chip design will be a big paradigm shift and is poised to bring about tremendous benefits to the design eco-system. However for the design community to actively adopt it, the relevant stake-holders need to look into it in a holistic way and much beyond the scalable and economic computing power and data storage combo.  And this may very well redefine the existing chip design methodology.

posted in Semiconductor, Business, Ecosystem, Cloud, chio design | 0 Comments

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