19th October 2005

Design trends & EDA tools : China & Taiwan

posted in EDA, Fabless, Survey |

I recently read the latest report from EE Times and Gartner Dataquest on Design Trends & EDA Tools : China & Taiwan. It can be accessed from their website http://www.eetasia.com.

The report makes a very interesting reading and made me ponder on a few points…….

ASIC Design segment

A. Application segment
While consumer applications remained the major application segment in Taiwan (as was in ’04 too), it displaced Telecom/Datacom in China to be the major one there too. Some possible underlying reasons (apart from generic market conditions) could be
· Telecom/Datacom designs have traditionally been using the leading edge process geometry. The rising mask costs associated with them could have been a factor of the decrease in new ASIC designs.
· The varied & vast set of categories within the consumer applications mkt. abets more ASIC designs and spin-offs.
· More consumer ASICs are coming out with the rapid growth of the China consumer mkt.

B. Gate Count
The general increase in the gate count follows the rising complexity which is also aided by the integration of various functions/categories in a single product.
Majority of the respondents working on large designs are companies that are local subsidiaries of foreign companies or local ventures – not joint ventures with foreign companies. This is mostly due to the high costs involved in large & complex designs. It makes sense for joint ventures with foreign companies to focus on the local marketing & enhance their foreign partner’s footprint in the local mkt.

C. Process Geometry
China figures indicate a more rapid embracing of newer technos.
The 0.18um in Taiwan, apart from remaining the predominant node for the past 3 years, has grown from 35% from last year to 44% while the 0.13um has increased from 13% to 23%.
0.18um is still the dominant node in China. However, it’s share has slightly decreased from 49% to 45%. But it’s in the 0.13um that we see the real increase – 12% to 31%

D. IP core usage rate
EDA companies’ share has decreased and has been correctly attributed to their partnering with foundries. With the increasing complexities and the focus going more towards Design for Yield, it is natural for foundries to play a major role in this partnership with EDA vendors/3rd party IP suppliers. The growing complexity of selecting the right IP & the subsequent issues seen during their integration in the design compel companies resort to developing them in-house. The marked surge in the independent 3rd party suppliers is also due the fact that they specialize in their niche IPs & these IPs are their main products.

EDA tools usage
Increasing reliability and reduced costs are the paramount factors for the electronic designers in Taiwan (increased functionality is no longer the most important goal) while increased functionality and reduced cost are the most important goals for the designers in China.

This possibly indicates a more mature market (in terms of EDA tools usage) in Taiwan where they seem to be more conversant and satisfied with the various functionality features offered by the EDA tools and hence are focusing more on reliability i.e. fewer issues while going through the design flow and hence shortening their time to market.
Cost reduction remains common; not surprising where Consumer applications is the predominant market.

This entry was posted on Wednesday, October 19th, 2005 at 7:18 pm and is filed under EDA, Fabless, Survey. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

Leave a Reply

  • Calendar

  • October 2005
    M T W T F S S
    « Sep   Nov »
     12
    3456789
    10111213141516
    17181920212223
    24252627282930
    31  

Search