5th December 2007

Decline in ASIC design starts

posted in Uncategorized, ASICs |

The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4 percent from 2006’s 3,408, according to market research company Gartner Inc. Of the 2007 ASIC design starts, about 200 starts made at 65-nanometer design rules or below.

A few interesting points from this report:

- In general ASIC design starts are declining. Exponentially increasing cost at leading edge plus a strong ASSP offering (which amortizes costs across multiple customers) are cited as the main factors. - Companies pushing leading-edge ASIC designs tend to be in high-performance computing, wired communications, high-end storage, high-end cellular phones and video game consoles.

- The average revenue per design and the average units per design continue to rise, resulting in overall growth in ASIC revenue.

- Designers in China are not using leading edge technologies; hence contribute to slowing of the overall ASIC start-ups’ decline.

- This also leads to China representing a market with ASIC growth potential.

- More ASIC design starts are predicted in Asia-Pac

Now, we have been talking of ASIC decline for the last 5-6 years. The question remains: is there any life left in the ASIC market? The answer is a provisional “yes.” as per  Hugh Durdan, vice president of marketing for eSilicon Corp, a fabless ASIC house and I am inclined to agree with him due to the following reasons:

- Inspite of overall decline in ASIC design starts, overall revenue is increasing. Big players like Cisco, Nortel and other major OEMs continue to use ASICs for differentiation

- While FPGAs have improved in their race to catch up (and substitute) ASICs, the gap still remains. Structured ASICs have tried to fill this gap but have had a mixed response from the industry and market. Till the industry figures out a way to address this gap, ASICs and FPGAs will co-exist

- The big ASIC players have come up with various approaches to revive this ASIC market. Some of them are:

- IBM, world’s no 2 ASIC supplier (after TI) maintains that they do not see any slow down. It rolled out its ASIC offering this year in 45nm techno which combines embedded DRAM with SOI technology. However, let me add that this is more geared towards niche & bleeding edge applications and the mainstream ASIC sector consists of products based on 130- and 90-nm technologies and the 65-nm ASIC market remains small. Also SOI is more costly than the traditional bulk silicon process and this may not help the mainstream ASIC market.

- Earlier this year, NEC Electronics rolled out the CB-55L, a cell-based ASIC technology built around a 55-nm process. Believed to be the world’s first logic device that utilizes a high-k dielectric film for the gate stack, it claims to reduce leakage current and improve power consumption by 40 percent over previous 90-nm devices

- Toshiba is readying its previously announced, 45-nm ASIC line. The technology is based on bulk CMOS, which it claims will outperform the SOI-based offering from IBM.  

This entry was posted on Wednesday, December 5th, 2007 at 11:35 am and is filed under Uncategorized, ASICs. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

There are currently 5 responses to “Decline in ASIC design starts”

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  1. 1 On December 5th, 2007, Ang Chew Hoe said:

    Have not be seeing your post for quite some time. Great to see your post again.

    Your view of ASIC vs FPGA is quite interesting. In my opinion, I believe FPGA will dominates since it is cheaper, offer faster turnaround and thus faster time-to-market. I also think FPGA tends to use higher end process technology, so the differentiation advantage of ASIC will be wash out if ASIC is designed for lower-end process technology.

  2. 2 On December 5th, 2007, meenu said:

    Thanks, Chew Hoe. Had been travelling and somehow got buried under..!!

    Although FPGAs have improved on all fronts, even the highest end FPGAs do not have the density, performance and high volume unit costs of ASICs. Plus there are issues on security/encryption.

  3. 3 On January 18th, 2008, Raju said:

    I would apprecaite if someone can give ASIC design starts stats per Geographic region. Will they increase in India/Asia and decrease in North America?

  4. 4 On January 18th, 2008, Meenu said:

    The latest and detailed stats may be available from payable reports compiled by various Research & Analysis companies like Gartner, iSupply etc.

    A couple can be found at these links (they may not be the recent ones)
    http://www.alacrastore.com/storecontent/markintel/SEMICO-50044704
    (But dated Nov 2006)
    http://www.alacrastore.com/storecontent/Business-and-Industry/172638064
    Report overview

    In addition, the following links may provide you with some Asia stats (note that these were done in May 2007)

    http://www.eetasia.com/ARTICLES/2007MAY/PDF/EEOL_2007MAY03_EDA_TA_01.pdf?SOURCES=DOWNLOAD (for Korea)
    http://www.eetasia.com/ART_8800463373_480100_babea70e200705.HTM (for China)
    http://www.eetasia.com/ART_8800463375_480100_4e573a61200705.HTM (for Taiwan)

    More ASIC design starts are predicted in Asia as compared to N.America. It’s to be noted, however, that this may not translate to higher ASIC revenues in AP w.r.t N. America

  5. 5 On March 22nd, 2011, Cicely Komara said:

    Instructive article. I enjoyed it very much! Thanks. Cicely Komara

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