The number of ASIC designs taping out in 2007 looks set to be 3,275 down 4 percent from 2006’s 3,408, according to market research company Gartner Inc. Of the 2007 ASIC design starts, about 200 starts made at 65-nanometer design rules or below.
A few interesting points from this report:
- In general ASIC design starts are declining. Exponentially increasing cost at leading edge plus a strong ASSP offering (which amortizes costs across multiple customers) are cited as the main factors. - Companies pushing leading-edge ASIC designs tend to be in high-performance computing, wired communications, high-end storage, high-end cellular phones and video game consoles.
- The average revenue per design and the average units per design continue to rise, resulting in overall growth in ASIC revenue.
- Designers in China are not using leading edge technologies; hence contribute to slowing of the overall ASIC start-ups’ decline.
- This also leads to China representing a market with ASIC growth potential.
- More ASIC design starts are predicted in Asia-Pac
Now, we have been talking of ASIC decline for the last 5-6 years. The question remains: is there any life left in the ASIC market? The answer is a provisional “yes.” as per Hugh Durdan, vice president of marketing for eSilicon Corp, a fabless ASIC house and I am inclined to agree with him due to the following reasons:
- Inspite of overall decline in ASIC design starts, overall revenue is increasing. Big players like Cisco, Nortel and other major OEMs continue to use ASICs for differentiation
- While FPGAs have improved in their race to catch up (and substitute) ASICs, the gap still remains. Structured ASICs have tried to fill this gap but have had a mixed response from the industry and market. Till the industry figures out a way to address this gap, ASICs and FPGAs will co-exist
- The big ASIC players have come up with various approaches to revive this ASIC market. Some of them are:
- IBM, world’s no 2 ASIC supplier (after TI) maintains that they do not see any slow down. It rolled out its ASIC offering this year in 45nm techno which combines embedded DRAM with SOI technology. However, let me add that this is more geared towards niche & bleeding edge applications and the mainstream ASIC sector consists of products based on 130- and 90-nm technologies and the 65-nm ASIC market remains small. Also SOI is more costly than the traditional bulk silicon process and this may not help the mainstream ASIC market.
- Earlier this year, NEC Electronics rolled out the CB-55L, a cell-based ASIC technology built around a 55-nm process. Believed to be the world’s first logic device that utilizes a high-k dielectric film for the gate stack, it claims to reduce leakage current and improve power consumption by 40 percent over previous 90-nm devices
- Toshiba is readying its previously announced, 45-nm ASIC line. The technology is based on bulk CMOS, which it claims will outperform the SOI-based offering from IBM.