14th
February
2007
Statistical tool avoids overdesign with excessive margins
posted in EDA |
A new tool in the DFM arena –
Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.
It promises 5 basic capabilities –
- Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
- Tradeoff analysis that lets users adjust specifications to impact yield
- Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
- Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
- Statistical visualization lets users explore and view the data.
Looks like a comprehensive set….
This entry was posted
on Wednesday, February 14th, 2007 at 2:55 pm and is filed under EDA.
You can follow any responses to this entry through the RSS 2.0 feed.
You can leave a response, or trackback from your own site.
