Statistical tool avoids overdesign with excessive margins

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –

  1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
  2. Tradeoff analysis that lets users adjust specifications to impact yield
  3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
  4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
  5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

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