Travelling On The Silicon Road

Ron Wilson, executive editor of EDN makes an interesting take on the low power SoC trend. He writes about the change in significance of low power design. Pre 90nm, low-power design was something you did in response to a specific application requirement. Post 90nm, according to tool vendors at least, low-power design is something you do so that the chip can work at all. This suggests that tools for invasive low-power design will be a gating factor in the industry’s migration to 65 nm and certainly beyond. And if there’s one thing that increases the–shall we say—intimacy of the relationship between the foundries and the EDA industry, it’s an obstacle to wafer shipments. 

I refer to this as yet another example of the expanding role & growing prominence of foundries. To fill their billion dollar fabs, they have to catalyse solutions for issues which may deter new design starts. So, if low power tools is a gating factor, they will “collaborate” with the EDA vendors. As I noted in an earlier post, Virtual vs. Vertical, it is the same for DFM; here too foundries started working together with the EDA vendors with information & data that was once under wraps. 

As they say, it is the economics!