Archive for the 'Foundry' Category

IPs and TSMC

Monday, October 15th, 2007

Fuelling the ambition to become a leading provider of chip design services and IPs i.e. in addition to the top post of pure play foundry, TSMC has acquired Ottawa’s memory IP start-up, Emerging Memories Technologies Inc. (EMT).  


EMT, a start-up with a relatively small group of memory technologists (and headed by 39 year old Sreedhar Natarajan) specializes in the design and licensing of leading-edge embedded memory technology in both bulk CMOS and SOI and was launched in 2004 when the memory design biz of Atmos Semiconductor was taken by Mosys. Many employees at Mosys moved to EMT – and now will move to TSMC.


As I noted in an earlier post on a similar topic in May this year - call it as seismic changes or consolidation, the chip manufacturing world is going through some upheaval.

EDA & Foundry

Wednesday, June 13th, 2007

Ron Wilson, executive editor of EDN makes an interesting take on the low power SoC trend. He writes about the change in significance of low power design. Pre 90nm, low-power design was something you did in response to a specific application requirement. Post 90nm, according to tool vendors at least, low-power design is something you do so that the chip can work at all. This suggests that tools for invasive low-power design will be a gating factor in the industry’s migration to 65 nm and certainly beyond. And if there’s one thing that increases the–shall we say—intimacy of the relationship between the foundries and the EDA industry, it’s an obstacle to wafer shipments. 

I refer to this as yet another example of the expanding role & growing prominence of foundries. To fill their billion dollar fabs, they have to catalyse solutions for issues which may deter new design starts. So, if low power tools is a gating factor, they will “collaborate” with the EDA vendors. As I noted in an earlier post, Virtual vs. Vertical, it is the same for DFM; here too foundries started working together with the EDA vendors with information & data that was once under wraps. 

As they say, it is the economics!    


OEM - Foundry Direct model??

Tuesday, June 12th, 2007

Slowing growth in semiconductors will drive new rounds of consolidation and partnerships as chipmakers seek creative strategies, according to Bryan Lewis from Gartner.  As reported in an article in EE Times, he talked about some systems makers experimenting with direct links to foundries, cutting traditional chipmakers out of the picture.

While the couple of examples cited in the article are by no means a sure indicator for this possible trend, there does seem to be a few signs leading to this path:

- Growing importance of DFM, and thus links between design & foundry

- TSMC’s growing role in developing IPs

Common Platform Agreement extended to 32nm

Thursday, May 24th, 2007

IBM and its Common Platform agreement partners will extend their development relationship to 32nm too.

The group started with 2 partners – IBM and Chartered. This later included Infineon, Samsung, and now Freescale. In addition, with the collapse of Crolles Alliance, it can also draw more partners.

While collaboration is a necessity in these process nodes and the Common Platform Agreement has been doing quite well, there have been reports (which subsequently have been dismissed as rumours) that the foundry vendors in the alliance are struggling with compatibility issues - and this can get compounded with increasing number of members.

TSMC catches up with Intel on 45nm production

Thursday, May 24th, 2007

So, a foundry has closed the gap with an IDM!

In all likelihoods, TSMC will be in volume production for 45nm at the same time as Intel – in first half of 2008. As noted by David Manners in an an earlier post, “With all this third party expertise soaking up the industry’s value-add, where is there to go for the IDMs?”

Singapore’s 5M$ wafer fab training program funding

Tuesday, May 8th, 2007

The Economic Development Board (EDB) has recently announced that it will invest over $5 million over the next three years into a program, Wafer Fabrication Specialist Manpower Program, designed to groom more wafer fabrication experts at local universities; aim is 300 new engineers to meet the chip industry demand.

The funds jointly contributed by the government and industry, would be used to provide monthly stipends of up to $710 to engineering undergraduates specializing in wafer fabrication in their final years of study at the National University of Singapore and Nanyang Technological University.

With more & diverse career options available to the students and the emerging of newer semiconductor/microelectronics hotbeds in the region, this program may help to address the manpower gap faced by the industry.

UMC joins CPF standard alliance

Monday, April 23rd, 2007

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

HSMC to chip in 4 bn$ for Indian fabs

Saturday, March 31st, 2007

I had reported in an earlier post “India outlines long awaited IC policy”, that the Indian govt.’s announcement of Special Incentives Package Scheme is likely to be followed by announcements by potential investors.

While SemIndia had already proposed investment in partnership with AMD, the latest one is from Hindustan Semiconductor Manufacturing Corporation (HSMC), a Silicon Valley-based semiconductor company. It has announced its plans to invest over $4 billion in chip foundries in India and has roped in Infineon as its technology partner; Infineon will license its 0.13u process techno and has said that it is open to considering an equity participation ‘subject to the final contract’.

According to a study by Frost and Sullivan, the semiconductor market in India is expected to grow from $3.25 billion in 2006 to $36 billion in 2015. The Indian govt. has announced Special Incentives Package Scheme, MoUs are being signed, what is to be seen now is the implementation of these plans and the coming up of the fabcities.

UMC to open support office in India

Monday, March 19th, 2007

UMC has announced that it plans to open a support office in Hyderabad, India. The main charter is to support India based customers. This is close on heels with TSMC’s setting up office in Bangalore, India.

TSMC sets up office in India

Tuesday, February 6th, 2007

TSMC has announced the opening up of its office in Bangalore, India with the primary mission of supporting its existing customers with design activities in India. They see a huge increase in the number of advance technology designs coming from India.

What surprises me is their delay till date. With no major advance tech fab in the country, delays in fab investments/policies and spurt of fabless design companies, there had long been the potential of strengthening biz thru local presence.

No major fab investments for India in 2007 - Gartner says

Thursday, December 14th, 2006

Gartner predicts that there will not be any major fab investments for India in 2007. There indeed is a lot of buzz for India in the design space. It has led to major collaborations as well as investments. Global contract manufacturers have entered with an eye on the huge local market potential. While a few consortia have plans, some of which have started on their first stages, it will take some time before any further significant investment is done towards setting up fabs and moving India to a design plus manufacturing hub.

Virtual versus Vertical

Wednesday, December 21st, 2005

Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.

DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.

With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.

Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty.

TSMC executive sees more IP from foundry

Tuesday, December 13th, 2005

To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?

Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.

It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.

So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?

Is Infineon going fabless ?

Friday, November 18th, 2005

One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.

It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.

The sifting is being done……..

India to take stake in fab project

Friday, November 4th, 2005

It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.

Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.

Consumer Era gives birth to "Gigafabs"

Wednesday, November 2nd, 2005

With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.

Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.

Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.

UMC’s Hu envisions a new model for foundry business

Wednesday, October 5th, 2005

Comments on “UMC’s Hu envisions a new model for foundry business” in Electronic Engineering Times by Ron Wilson

While it’s true that the leading foundries in this age must have the capabilities of an integrated device manufacturer, the transition from foundry to solutions provider is not an altogether new biz model nor is it an entirely different vision for foundry companies.

Quite a few years back, when foundries, especially in Taiwan, realized that low cost was no longer sufficient for their intended growth, they started focusing more on their IP portfolios. Design support also evolved into working on actual design issues and in some cases offering design services.

To cite a few……
TSMC offers IP portfolio, Design Centre Alliance, In house and 3rd party library services and Assembly & Testing services to some extent.
Chartered offers IP Access & Design Access.

Some are transitioning into this model with 3rd party collaboration while some try to develop it in-house. Foundries also hold an additional advantage in addressing DFM issues.