Travelling On The Silicon Road

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, “Wherever the industry takes CPF and UPF, if the users want it, we’ll do it. If you’re a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it’s CPF or UPF or some common thing in the future doesn’t matter any more. We’ve got the software system that will build the chips, and we’ll follow wherever the standard goes.”  

Let’s see what follows from the rival potential standard’s camp……

Intel is hogging the silicon limelight with it’s news on the technology breakthrough - usage of high-k and metal gate transistors for 45nm technology.

Scaling without losing out much on leakage is the driving advantage. The major advantage, though, is that with this technique, Intel will not have to significantly change its current production process. This is different from the alternative solution being disclosed by IBM and its partners. The latter involves SOI which is a more expensive production technique and they plan to later switch to immersion lithography. Another lead for Intel is that the production with this new technique starts mid this year whereas IBM plans production in end 2008.

Having said that, it still appears that while Intel has stolen the lead in announcing the breakthrough with earlier production planned (and that too across servers, desktops and laptop applications), IBM will have a long term advantage as its technology involves integration of the metal gates so that they are embedded in silicon as compared to Intel where they sit atop a proven silicon architecture – thus solving long range problems and more future transitions.

Another salvo to Crolles2 Alliance. After NXP’s announcement on its exit from Crolles2 Alliance, comes the statement from Freescale that it is joining the IBM Alliance.

Apart from investing in leading edge chip R&D, some of the potential benefits for Freescale in this alliance are leveraging capacity at Chartered and possible wireless co-development efforts with Infineon. Freescale also expects to significantly accelerate its SOI roadmap with this IBM partnership.

This leaves STM as the lone original member of the Crolles2 alliance. A potential new partner will need to have deep pockets to fund expansion of the group’s 300mm fab as well as work on 45nm and beyond processes. This is apart from a good fit from the technology standpoint. TI is touted as one of the possible candidates. However with the latest announcement from TI to end leading edge digital logic process development at 45nm and rely on foundries is set to have important implications on this.

Cadence’s primary EDA rivals felt that Power Forward Initiative introduced by Cadence in May ’06 wasn’t open and inclusive and joined another coalition – Accellera UPF effort in Sep. Si2’s Low Power Committee (LPC) was set up in Oct as an attempt to bridge the gap and address users’ requirement of having a single low power specification format.

Si2 first approved CPF 1.0 saying that its approval of CPF 1.0 does not constitute taking sides and that they have declared it as a “specification” and not a “standard”. This may be a conciliatory offer to Accellera which said that they are actively working with Si2 to converge UPF and CPF into a single standard. Then Si2 issued a RFT to complement the CPF and Cadence in its response has now provided them the source code of its CPF 1.0 parser; in the process opening the door to tool implementation that supports CPF ……. and hence giving another push to boost their format

In its new avatar, Philips Semiconductor, now NXP exits Crolles2 Alliance, a partnership formed in 2000 and renewed in 2002, and teams up with TSMC.

As we further scale the technologies and the fab and associated costs increase, alliances is no longer an option; it’s mandatory. Amongst the present big ones, the Chartered, IBM, Samsung, Infineon alliance seems to be the more promising one overall. IBM is also reportedly in talks with the other two Crolles2 partners, STM and Freescale, to join Crolles2 Alliance.

Freescale had been pushing to get IBM into the Alliance while STM was pushing for TSMC. NXP has an asset lite strategy (it plans to increase its outsourcing ratio to 40% by 2010, from its present 10-20%) and it seems logical for it to strengthen its cooperation with its long time foundry partner, TSMC.

A boost to SSTA…..Altos has introduced Variety, a SSTA library characterization tool. While there do exist similar tools in the market, Altos’ niche factor is that it supports multiple formats (unlike Cadence, Synopsys, IBM, Magma etc. which support only their proprietary formats). This is definitely an advantage as it gives flexibility to the user to switch across various flows/vendors.

Characterization speed and accuracy, the two most important aspects in library characterization, are something which Altos promises through this tool.

While launching iTV, Apple CEO, Steve Jobs mentioned, “Apple is in your den, in your living room, in your car, and in your pocket, I hope this gives you a little bit of an idea of where we’re going.”

Now a few months down the road, Apple has indeed added another gizmo for the pocket by introducing iPhone. Yet another player in the mobile phone/smart phone market. This time, however, as it is from iconic Apple, expectations are bound to be (“ahem”) a bit different – stylish, user friendly and features rich??

Waiting to see whether iPhone will have the same success as the iPod….
Apple’s shares have already registered a 6.7 % increase with the latest product launches – first Apple box/iTV and now iPhone.

A highly interesting article in Electronic Business by Tam Harbert.
Private equity firms target cash rich semiconductor entities, leverage on its cash flow to borrow more funds and then restructure, improve the company’s bottom line and then sell it or take it public; providing returns of 30-40%. Tam lists the reasons behind recent LBOs in the semiconductor space – industry being driven by the less cyclic consumer market, transition to fab-lite/fabless models and a better control over inventory.

The question which arises is that why hasn’t the chip industry taken the necessary steps to consolidate and leave that task to the private equity guys? iSupply’s Derek Lidow cites portfolio management as the reason. While chip companies, usually run by engineers structure the portfolio on technology, private equity folks tend to manage groups of products on market segments and geographical regions; rather than technology criterion. They acquire and merge companies that have similar product portfolios.

While on mergers and acquisitions, Mentor Graphics’ CEO, Wally Rhines mentioned in a recent article that the role of acquisitions in EDA industry is set to change. As the acquisitions in the past few years have failed to garner commensurate market capitalization, he opines that companies will either pay less for acquisitions or stop making them.

Gartner predicts that there will not be any major fab investments for India in 2007. There indeed is a lot of buzz for India in the design space. It has led to major collaborations as well as investments. Global contract manufacturers have entered with an eye on the huge local market potential. While a few consortia have plans, some of which have started on their first stages, it will take some time before any further significant investment is done towards setting up fabs and moving India to a design plus manufacturing hub.

Yet another DFM tool in the market.

DFM Blaze announced a DFM tool, Blaze IF, to address topology variations caused due to CMP. It intelligently inserts dummy metal fill patterns into a design layout taking into account not only the design requirements like power and timing needs, but also the electrical issues like signal integrity and IR drop – which traditional approaches to metal fill do not accomplish.

This is in addition to the announcement of Blaze MO, announced earlier this year which provides guidance to OPC tool used in manufacturing through an annotation layer in the GDSII database. The tool optimizes the design by small tweaking of the gate lengths (within the process limits) for reducing leakage power and improving timings and provides this guidance to the OPC tool.

All these aim to bridge the gap between design and manufacturing. Instead of a blanket set of rules for the complete design, design specific and design objectives’ relevant optimizations are carried forward to the manufacturing. Making it an integral part of the flow before handoff to manufacturing is a step closer to address issues arising out of the open loop caused by changes made to the design after handoff – oblivious to the design issues which may be impacted.

In October 2005, John Chambers, Chairman and CEO Cisco Systems had announced a 1.1 B$ investment in India. In his recent visit to India last week, he re-iterated Cisco’s commitment while outlining the importance of India in Cisco’s global growth strategy.

Cisco’s key investments in India include a new R&D campus in Bangalore, increasing by threefold its local workforce, launching a manufacturing pilot facility for local market and allocating funds for venture capital investments in high growth and nascent companies based in India. Investments are expected in companies involved in broadband content and digital media.

All these are in line with John’s vision of the network becoming the platform for all forms of communication and ICT – also the topic of his interesting talk in Singapore last Friday.

Qualcomm, with its IFM (Integrated Fabless Manufacturing) strategy is quietly but steadily decreasing the gap between itself and IDMs in new process adoption time. The world’s largest fabless design company is leading the way in how the fabless design community needs to overcome the DSM hurdles of the widening gaps between IC design and manufacturing flows.

While not exactly striving to be process experts, Qualcomm has formed a virtual manufacturing organization including its VLSI Technology organization and DFX unit which has helped it to understand, appreciate and thus resolve a host of complex and costly issues. The results, closing of the technology gap with the IDMs, are the proof.
They are cautious enough, though, as to not necessarily be the first ones to ship out a new product on a new technology node.

With Paul Jacobs’ strategy of making people understand that Qualcomm is a wireless technology company and not just a CDMA company, it needs all the efforts and results to zoom to the next node in a competitive manner.

An interesting take on the EDA industry evolution and look into the trend by Leon Stok, director of EDA for IBM’s Systems and Technology Group in a keynote address at the International Conference on Computer Aided Design (ICCAD).

Stok identified three previous innovation eras in the EDA industry — those of invention, implementation, and integration. The fourth era, he said, is the one we’re about to enter and is centered on design implementation “platforms”. To make platform innovation happen, Stok said, we will need to define standards as APIs, not ASCII formats. This will allow tools to talk to each other, instead of producing data that another tool can barely read, he noted.

With APIs, smaller companies with innovative potential solutions for the UDSM technology challenges will have a more level playing field. Each can plug in their solutions and then let the market forces decide. It will also pave the way for the bigger players as they too can focus on the overall user flow with a market decided mix of their own in-house tools or point tools from other companies.

The organizers of ICCAD (International Conference on Computer Aided Design) decided to do something different and added a designer’s perspective track this year.

“Our goal is to bridge the gap between practitioners and research,” said ICCAD general chair Soha Hassoun, an associate professor of electrical engineering and computer science at Tufts University (Medford, Mass.), in opening remarks at the conference. “We would like them [designers] to tell you [researchers] what critical issues should drive CAD research in the next few years.”

Now, I would term this as going back to basics. The users tell their requirements to the researchers which in turn guides the researchers towards the right direction in terms of practical benefits and usage of their efforts – optimal Lab to Fab transition.

Another tenet emphasized was by STMicroelectronics’ Pascal Urard: “We need academia and the EDA community to think at the flow level, not only at the tool level”.

It is apt to remind the EDA community that they should enable the end user with his final flow and not only the point tools. It’s true that tools provide the differentiating edge amongst the EDA vendors and users should have the flexibility of picking up the ones which best suit his flow.

However, to justify the “Automation” in “EDA”, it pays to facilitate the flow.

Atheros recently picked up Attansic Technology, a designer of Ethernet chips in Taiwan for its Gigabit Ethernet technology for 802.11n market. Attansic is a subsidiary of Asustek. Craig Barratt, CEO of Atheros said, “there has really been tremendous growth in companies in Taiwan doing pretty impressive R&D, creative engineering and product development.”

Moving to India – India needs to include IPs and technology know-how into their growing expertise portfolio. As I mentioned in an earlier post, product know-how is essential for the differentiating factor. With its relatively better copyright rules as compared to China for example, if the Indian companies can supplement their design skills and embedded software expertise with the product & technology know-how, they can raise the stakes higher.

There are some examples like Wipro, Tejas Networks etc. but it’ll be good to see this list grow.

From what had earlier started as point engagements or doing auxillary services, semiconductor design companies in India are now working on not only the leading edge technologies (which they were still doing in the past as point engagements) but also end to end projects. In doing so, the Indian design engineers have been able to broaden their skill set as compared to quite a few of their international counterparts.

When you don’t have the so called luxury to specialize in certain niches areas and are thrust with the responsibility of doing multiple design tasks in order to get a design out, well, one learns and that too fast! A positive go-getter attitude coupled with a survival instinct honed by the competitive Indian environment (which starts right from kindergarten) also does help.

The early 90’s saw design companies in India getting supplementary work albeit some in leading edge technology. Of course, cost was the major reason. Once they instilled some confidence, it morphed into a bigger part of the design cycle. They started getting not only more designs but the opportunity and the responsibility to execute a design end to end and also complex designs. However technology innovations have still not figured within their purview.

Attrition: While this rate is high and experienced engineers switch jobs, money is not always the major deciding factor. Generically speaking, fresh graduates/ engineers with a couple of years experience rate the work quality and the company branding more than money. Mid range experience engineers value work quality, responsibilities and money. Professionals who return to India after working abroad are looking for challenging opportunities. I am not saying that money is not significant but rather that if the employee retention logic is through money alone, well, mate, you are throwing the wrong carrot…Indians have always had an entrepreneurial spirit (I attribute it to the urge to remove the shackles, something linked with our political history as well as the present political scenario).

Design ecosystem: While some may say that the absence of fabs is not a hindrance to the design scene in India, the fact remains that SoCs of today are not just built on design flow, IPs and library know how. One needs to have the product know how too – and this can become a major differentiating factor. And of course, trying out a new design concept in one country, fabricating in another and waiting for it to come back in order to do the tests, not to mention the red tape which may be involved, is something which one can do without. One of the reasons why Taiwan grew to a semiconductor hub is that it had design, fabrication, packaging and testing right there. So, while presently it may not sound so much of a missing link, it will gain importance if India is to take up China.

The above article was preceded, by just a couple of days, by another article appearing in Electronic business cited India’s niche: semiconductor design services. So if the talents void increases, India risks losing the niche.

With technology advances, more & more features are being incorporated in the mobile phone. And the existing features are being further refined e.g. increasing video and audio quality and PDA functions thrown in. While this entices the young generation, executives as well as techno geeks across various generations and the upward swinging classes, there still remains two main chunks of a country’s population waiting to be tapped - the rural or economically backward set and the other is the senior citizens club – and both exist in all countries.

China and India with the world’s largest and second largest populations of course provide the maximum growth potential. The difference is in the 2 categories. While the rural/economically backward class will opt for a no frill mobile as their first set of mobiles or as an entry point in climbing up the economic ladder, the senior citizens will opt for it for the sheer reason of convenience and ease to handle. A small mobile bundled with the latest technology for camera, PDA functions, audio etc. is not of much use to them especially if they have to pound the miniature keys – not an easy task with age taking its toll on their movements and eye-sight. What they need is a simple robust instrument able to do the basic functions and perhaps with a little bit of audio, camera and games thrown in – at an affordable cost – remember they have retired. And the size should be small enough to be held conveniently in their pockets or hung around their necks but not so small so as to make them lose it.

Both sets require low cost phones and this is where single chip solutions hold an edge. And as pointed out in the article, chipmakers lacking single chip solutions will face increasing pressure to compete with those that have them.

This makes for an observation here – why are the mobile companies not targeting the older generations especially in the developed countries like Japan and some European countries where the ratio of senior citizens to youth is quite high…..???

This was the questioned posed by Chairman of Orb Networks and former CEO of Cadence, Joe Costello in his DAC 2006 keynote speech.

The “it” referred to here is the mix and match of new plug-ins (internal and external), bundling things on top of others’ offerings and selling directly to customers.

With the increasing complexity of technological challenges compounded by rising market pressures, it does indeed benefit both the big EDA companies as well as the small start-ups with niche solutions to collaborate. However, opening the tools and making them pluggable is not without its major share of teething issues. While standards do take a long time to be formulated and then adopted, they’ll still be required to an extent for “universal plug-ins”.

One scenario is where EDA companies have the basic engines for the standard design activities. To these, smaller niche companies provide their plug-ins for value-addition and tackling of issues related to leading edge designs. With a uniform standard, these companies can go with their plug-ins to various EDA companies. In its absence however, each EDA company will need to work closely with these smaller companies and sell the complete “bundle with options” to the user.

A point to be noted here is that it’ll be naïve to assume that the present basic engines are implemented in a modular fashion where a plug-in can be used in a quasi seamless fashion. Then comes the question: if addressing of the leading edge issues is done in a modular fashion by the smaller companies who are free to sell their wares to the other big EDA companies, what is in it for the big EDA companies? What will be their competitive edge? But on the flip side, if the major EDA companies persist in attempting to do everything on their own, given the complexities and constraints, it’ll not result in much growth for the EDA industry.

Interestingly, there are signs of the industry moving in this direction. For DFM, with TSMC sharing their process information with the EDA companies to integrate into their design flow is one example. This can be treated as a “plug-in”.

Let’s take an example here: Synopsys recently came out with 3 tools in the DFM space - LCC (lithography compliance checking), CMP (chemical-mechanical polish) checking, and CAA (critical-area analysis). As per the press note, LCC inspects GDS-II files using a rapid-computation model of the lithography process, calibrated with foundry data. This scan predicts the actual shapes the mask features will produce, across the focus window of the lithography step. It then examines these features against a rule set to detect pinch-off, end-shortening, bridge, and other faults that could occur with a reasonable probability.

The normal output of the device is a color-coded die map: green for areas that pass, yellow for areas of concern, and red for trouble spots. Design teams that are knowingly pushing the litho rules can look under this graphic presentation at a numerical database that will give them actual predictions of critical dimensions.

Designers can then invoke an auto-correction tool, which is based on extensive, process-dependent heuristics, to deal automatically with the majority of the problems—adding space between lines, moving edges or corners, and other such reasonable measures.

Now reconsider the situation with a small EDA company working on the basic LCC part. It takes inputs from the lithography process model provided to it by the big EDA vendor (I don’t think the big foundries will be that comfortable in working closely with the smaller companies in handling their process data!). The GDSII is also provided as an input from the big EDA vendor’s tool(s). Finally the auto correction tool can be provided by either.

I cite this example because while these three new tools do attempt to handle the first order problems, they do not even begin to cover all the important sources of variation in 90-nm and finer geometries. TSMC cites more than 2000 independent sources of potential trouble.

I see a hybrid approach in the near future………

As pointed out in the article, most designers treat IP as a product. However, this product rarely comes with a guarantee; which is not that surprising. It’ll be almost suicidal given the argument that IPs are not plug in objects. Not only the IP’s functionality but also its interface and integration with the other components in the system determine whether the chip will work or not. And a standalone guarantee for an IP does not hold much credence.

A close working relationship between IP supplier and user has always been deemed vital for the successful IP usage and integration; hence to formalize it and bundle things under the “service” umbrella will not be that major a leap of faith.

China Syndrome cooling, an article by Ed Sperling in Reed Electronics points out the possible waning of the “Invest in the Booming China Market” wave by electronics companies. Possible reasons cited by them for hedging their bets in other regions and in other countries include:

- China’s emphasis on allowing other cities besides Shanghai and Beijing to partake in the economic revolution is making it far more difficult for companies to manage logistics between their manufacturing sites inside of China;

- Rapidly rising labor costs are forcing some companies to consider comparable wage scales in places such as Vietnam, Malaysia and Eastern Europe;

- China’s ineffective policing of intellectual property theft has made many companies reluctant to move design operations there;

- Continued U.S. government regulations about what technology can be shipped into China or developed there has kept the lid on many companies’ plans;

- Manufacturers are looking to hedge their bets with backup strategies in case of a natural disaster or political issues that can affect regions.

Well, it makes economic and political sense for China’s emphasis to let its cities other than Shanghai and Beijing to invite investments so that they can have an inclusive growth – something vital for both the economic and political stability of a country else the economic disparity thus created would mitigate the growth achieved otherwise. To help the electronics companies, infrastructure improvement in these other cities could help.

Ineffective policing of IPs is indeed an important deterrent. However a few recent events are providing some progress. Hong Kong Science and Technology Parks Corporation (HKSTP) recently inaugurated the Intellectual Property Servicing Centre (IPSC) at the Hong Kong Science Park. Based within the Hong Kong Integrated Circuits Design Centre at the Park, it offers IP licensing, IP hardening, IP integration and IP verification services. Most notably, IPSC is run by HKSTP and will make use of Hong Kong law for any legal dispute over intellectual property. A key vehicle for this will be the Hong Kong International Arbitration Centre which is based in the SAR.

Under the “7+1” IC Design Centre framework signed with the High-Technology Research & Development Centre of the PRC’s Ministry of Science & Technology, HKSTP jointly collaborated with Harbin Institute of Technology, Hefei University of Science and Technology, Zhejiang University and the Hong Kong University of Science and Technology in July 2005 to extend the SIP trading platform throughout Greater China. The collaboration is to develop a due diligence platform in legal and technical terms for SIP certification and authentication purposes.

In October 2005, HKSTP also formed alliance with the China’s Ministry of Information Industry Software and Integrated Circuit Promotion Centre (CSIP) for the Mainland China IC design industry. The alliance is to promote the cooperation and development of Mainland China’s IC enterprises under the guidance and supervision of the administrative bodies, to jointly facilitate the outreach and popularization of SIP in SoC design services, as well as to standardize the SIP design, SIP standard promotion and SIP protection mechanism.