Travelling On The Silicon Road

IBM and its Common Platform agreement partners will extend their development relationship to 32nm too.

The group started with 2 partners – IBM and Chartered. This later included Infineon, Samsung, and now Freescale. In addition, with the collapse of Crolles Alliance, it can also draw more partners.

While collaboration is a necessity in these process nodes and the Common Platform Agreement has been doing quite well, there have been reports (which subsequently have been dismissed as rumours) that the foundry vendors in the alliance are struggling with compatibility issues - and this can get compounded with increasing number of members.

So, a foundry has closed the gap with an IDM!

In all likelihoods, TSMC will be in volume production for 45nm at the same time as Intel – in first half of 2008. As noted by David Manners in an an earlier post, “With all this third party expertise soaking up the industry’s value-add, where is there to go for the IDMs?”

Call it as seismic changes or consolidation, the chip manufacturing world is going through some upheaval. While on one end, quite a few IDMs are transitioning to a fab lite strategy (albeit in different flavours) - especially with the high costs & risks involved in sub 65nm, on the other end heavyweights like TSMC are spreading their reach into the IP arena too.

As I noted in an earlier post, TSMC is leveraging on its resources and market reach.It may start off as “strengthening the design collaboration for critical sub circuits” (who doesn’t want FTSS??) but the intensity of the move has been enough to spread ripples in the till now independent IP biz world. By doing so, TSMC may well be doing its share in mitigating some of the risks involved in DSM design and thus catalyzing more of these design starts; and subsequently fill up its high-end fabs.

In the recent spate of takeovers by the private equity world and at a time when the chip industry is undergoing consolidation, a blip has occurred – Temasek Holdings’ wholly owned subsidiary, Singapore Technologies Semiconductors Pte Ltd. (STSPL) has failed to complete its attempted buyout of test and assembly provider STATS ChipPAC Ltd. STSPL now has a majority stake of 83.1 percent in the company, falling short of the 90% required to make STATS ChipPAC completely private

Cadence is slated to release its Low Power Methodology Kit in late June. The highlight of the kit is a wireless “representative design” implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design has sample IP including a processor and bus fabric from ARM, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm low-power memories from Virage Logic and 65nm technology libraries from TSMC.

While till date, EDA vendors have been mostly dishing out different point tools to address the industry’s power concerns, a big challenge is to help designers utilize the appropriate low power techniques and tools effectively and seamlessly within their flow on a real design – and in a timely manner. They need to be aware of the trade-offs required and some balancing tips to make the exercise productive.

A representative design is a step forward in this direction. The objective may be to regain the lead in the format war, but if it helps the end user, it definitely signals well!

Renesas seems to be bucking the trend of IDMs relying more and more on foundries for advanced process technology development.

Renesas believes in working (on its own or in collaboration) on advanced process development. With plans to increase sales in system-on-chip solutions and microcontrollers, it may make sense to keep the advanced process development in-house in order to have more control and direction for their major product offerings.

This, however, will not prevent it from outsourcing for volume production on advanced devices

Mark LaPedus reports in his article in EETimes about TI’s approach towards IC manufacturing – while bolstering its in-house effort in analog production, TI is shifting more of its logic based work & process flow to foundries.

TI is adopting a 3 pronged approach based on its product categories - At the 65-nm node, TI has three foundry partners for its wireless chips: Chartered, TSMC and UMC. For wireless chips at 45 nm, TI will continue to use UMC and TSMC. For DSPs, TI develops the processes & makes its own 65nm DSP. However it will rope in TSMC too for the next node. TI has been manufacturing Sparc processors for Sun; a foundry, probably UMC, will take over production at 45nm.

Shifting the responsibility of digital processes to outside foundries, while focusing on analog processes for in-house manufacturing does seem to be the right direction, especially now when the production costs & risks are escalating. However, this is not an all together new approach. If I recollect well, STMicroelectronics had followed this approach along with TSMC. While the base/digital process was same across the two companies, STM developed its own spin-offs e.g. analog, high power, RF for and based on its market requirements.
The advantages are: risk sharing (in certain cases, offloading) in base process, retaining its niche in customized or spin-off processes and having the second source options when capacity is needed.

The article mentions that by using leading-edge foundries, fabless Qualcomm Inc. has been able to close the manufacturing gap with rival TI. I would say that it wasn’t just using leading edge foundries; it was close co-operation with multiple leading edge foundries coupled with the adoption of what it termed as Integrated Fabless Manufacturing Strategy (IFM) that helped Qualcomm. As I noted in my earlier post, “Fabless Qualcomm zooms to next node“, (incidentally a comment on another article by the same author!) Qualcomm developed its own virtual manufacturing organization.

According to a news report, LSI Corp. is considering whether or not to continue its Consumer Electronics (CE) business. It was however clarified that this would not impact the company’s focus on its chips for mobile phones.

This comes closely on the heels of the revelation by LSI Corp. that it repurchased 5 million shares, worth $43 million, of its common stock in the past couple of days following its stock tumbling more than 12%; investors sold off the stock following the chipmaker’s April 25 earnings report, in which LSI said its sales for the quarter ending in June would fall $100 million of Wall Street’s expectations

While 60% of the revenue of the new combined company ((LSI Logic finalized its merger with Agere Systems in April and the new entity is called LSI Corp.) continues to come from its storage chips and systems business, does it mean an inclination of LSI Corp. towards the strengths of Agere Systems i.e. communications, networking and mobile phone industry?

While CE is generally considered to be a major revenue generator, it is not exactly a smooth sailing - decreasing market window, multiple features, growing design & packaging complexity, falling ASPs and convergence are some of the existing challenges

The Economic Development Board (EDB) has recently announced that it will invest over $5 million over the next three years into a program, Wafer Fabrication Specialist Manpower Program, designed to groom more wafer fabrication experts at local universities; aim is 300 new engineers to meet the chip industry demand.

The funds jointly contributed by the government and industry, would be used to provide monthly stipends of up to $710 to engineering undergraduates specializing in wafer fabrication in their final years of study at the National University of Singapore and Nanyang Technological University.

With more & diverse career options available to the students and the emerging of newer semiconductor/microelectronics hotbeds in the region, this program may help to address the manpower gap faced by the industry.

Read some interesting trivia in a book, “The Silicon Boys” by David A. Kaplan on origin of “bug” i.e. a computer bug….

The University of Pennsylvania’s ENIAC (Electronic Numerical Integrator and Computer) in 1946 was the first attempt at a large scale digital computer. It was a huge thing and had 18000 vacuum tubes. The warmth & light of ENIAC’s tubes presented a problem – moths liked them and would trigger short circuits. Hence “computer bug” meant a problem inside and “debugging” meant fixing it!

I read an interesting article on the recent iSuppli European Briefing series held in Hungary and reported by Drew Wilson in Electronic Business.

While iSupply sees consumers with 2 main devices: one handset for communications & information and the other one for entertainment with internet, gaming, music & video, Nokia forecasts the merging of all useful functions into one gadget. Its senior analyst also predicts the death of the stand alone camera.

Ideally users would gravitate towards a single device. However, categorizing “useful functions” is a formidable task. Consumers will weigh the pros & cons of the category contents. Ease of use, cost, weight, form factor, features available vs. used, services available & related logistics to use those features, product life time etc. are just some of the variables entering the picture. As a user, I would prefer a single device but not at the cost of sacrificing on ease of use of my “basic functions” requirement. e.g. my phone can have the latest add-on features but if the OS hangs or access time is long or I’ve to dig deep into my pockets to pay the service provider and with newer versions popping into the market before one even familiarizes with an older model- well that’s one road I’m not likely to tread on.

While I see one set of people converging to a single device, I see a not insignificant market (rather a bigger chunk) which would opt for 2 main devices. The low-mid end standalone digital cameras will become obsolete as the technology develops and costs come down. But that in no way signals the demise of high end standalone digital camera. People will still likely take the standalone camera for their holidays and serious clicking leaving the on-impulse shots and convenience pics to the converged portable device e.g. their mobile phone with camera.

The other interesting point highlighted was the change in biz model. The huge market comes along with myriad standards, IPs, tech know-how and more stake holders from varying & multiple sectors. The challenge will be to pave a seamless integration path. This will be mandatory given the life-cycle & competitive costs of consumer products

Synplicity rolled out its Synplify DSP ASIC Edition software at the Design Automation and Test Europe conference in France. Their earlier ESL synthesis tool was aimed at FPGA designs. With this new offering, they are targeting customers who use FPGA prototyping for their DSP based ASICs.

Another recent news has been that TSMC is broadening its IP portfolio giving worries to IP providers and speculation in the industry whether TSMC is moving towards ASIC like biz model.

Gives a new meaning to the phrase “ASIC demise”………

TSMC is broadening it’s portfolio of internally developed IPs and 3rd party IPs. It had started a program called IP-9000, later renamed to Active Accuracy Assurance Program, to qualify various IPs in its foundries. The objective was to expedite the design time with silicon proven 3rd party IPs.

With shorter design cycle time and with IPs becoming mandatory blocks in a design, the need for silicon proven IPs is not just desirable but also essential. Having a broad and quality IP portfolio is a big asset. If TSMC is getting into the ASIC like biz model, then indeed it is worrisome for the 3rd party IP vendors; especially the smaller ones who aspire to gain market share on the basis of their expertise in niche areas. The field gets all the more “unlevel”. But then it is a competitive world and TSMC would be leveraging on its resources and market reach.

A point to be noted is that, does this mean the resurrection of ASICs - often ranted about as dead ??

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

TI’s CEO & President, Rich Templeton, mentioned the importance of medical equipment biz for India’s semiconductor industry during his visit to India.

Applications in the medical area, along with automotive applications hold prominence in the near future for the semiconductor industry in general, albeit a lot more in emerging markets like India and China. While consumer and telecom applications still remain strong contenders and are mainstream applications, the potential for these emerging segments is huge.

The shortened market window & pricing pressures for applications like entertainment/computing etc. falling under the generic consumer umbrella doesn’t give a leveling field to the smaller or niche players. This is where these yet to be fully tapped markets like medical and automotive hold the lure. Emerging market with strong potential which does not necessarily require the leading edge process ….. these can very well also pave the way for process choice in the soon to be set up foundries in India.

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

I had reported in an earlier post “India outlines long awaited IC policy”, that the Indian govt.’s announcement of Special Incentives Package Scheme is likely to be followed by announcements by potential investors.

While SemIndia had already proposed investment in partnership with AMD, the latest one is from Hindustan Semiconductor Manufacturing Corporation (HSMC), a Silicon Valley-based semiconductor company. It has announced its plans to invest over $4 billion in chip foundries in India and has roped in Infineon as its technology partner; Infineon will license its 0.13u process techno and has said that it is open to considering an equity participation ‘subject to the final contract’.

According to a study by Frost and Sullivan, the semiconductor market in India is expected to grow from $3.25 billion in 2006 to $36 billion in 2015. The Indian govt. has announced Special Incentives Package Scheme, MoUs are being signed, what is to be seen now is the implementation of these plans and the coming up of the fabcities.

Read this article (Nadamuni says, in EE Times) ; Wanted to submit my comments there but looks like a perpetual error while submitting comments…..

2 issues which could be of concern to the fledgling Indian semiconductor market are: potential overcapacity situation and offering an attractive pricing strategy in face of strong competition from established regional foundries.

Investing with new equipment in light of the above and especially with the unavailability of incentives for such plants i.e. with second hand semiconductor equipment will make the potential investors wary.

However, having said that, if India were to offer the same set of incentives for second hand semicon equipment too, it’ll take a long time for it to catch up with cutting edge technology fabs as well as to address the design needs of the local design houses which have emerged from working on trailing edge technos to the leading edge ones.
Perhaps, a different set of incentives could work……???

UMC has announced that it plans to open a support office in Hyderabad, India. The main charter is to support India based customers. This is close on heels with TSMC’s setting up office in Bangalore, India.

There were some very interesting insights from the commentary on the panel discussion on the above topic.

People have been long talking about the demise of ASICs….and these are still around. A good starting point taken, hence, was the definition of ASICs itself. ASICs have undergone a transformation over the years and have evolved much from the traditional cell based ASICs.

Some interesting comments raised included:

- why have ASICs survived? Inspite of ridiculous prices, extremely unreliable and extremely unpredictable. Because they are needed. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing (Sherwani/OpenSilicon)
- Architecture is the key. More integration is not necessarily the right solution (Massabki/ChipX)
- How outsourcing and offshoring of basic R&D is affecting ASIC biz (Sherwani)

When we talk about ASICs declining, what are we referring to? Is it the number of design starts? And if so, which designs does this number include: cell based ASICs, embedded array, structured ASICs? Is it the total revenue?

Without a clear definition and specific measuring criteria, blanket statements do not make much sense.