Travelling On The Silicon Road

TSMC is broadening it’s portfolio of internally developed IPs and 3rd party IPs. It had started a program called IP-9000, later renamed to Active Accuracy Assurance Program, to qualify various IPs in its foundries. The objective was to expedite the design time with silicon proven 3rd party IPs.

With shorter design cycle time and with IPs becoming mandatory blocks in a design, the need for silicon proven IPs is not just desirable but also essential. Having a broad and quality IP portfolio is a big asset. If TSMC is getting into the ASIC like biz model, then indeed it is worrisome for the 3rd party IP vendors; especially the smaller ones who aspire to gain market share on the basis of their expertise in niche areas. The field gets all the more “unlevel”. But then it is a competitive world and TSMC would be leveraging on its resources and market reach.

A point to be noted is that, does this mean the resurrection of ASICs - often ranted about as dead ??

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

TI’s CEO & President, Rich Templeton, mentioned the importance of medical equipment biz for India’s semiconductor industry during his visit to India.

Applications in the medical area, along with automotive applications hold prominence in the near future for the semiconductor industry in general, albeit a lot more in emerging markets like India and China. While consumer and telecom applications still remain strong contenders and are mainstream applications, the potential for these emerging segments is huge.

The shortened market window & pricing pressures for applications like entertainment/computing etc. falling under the generic consumer umbrella doesn’t give a leveling field to the smaller or niche players. This is where these yet to be fully tapped markets like medical and automotive hold the lure. Emerging market with strong potential which does not necessarily require the leading edge process ….. these can very well also pave the way for process choice in the soon to be set up foundries in India.

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

I had reported in an earlier post “India outlines long awaited IC policy”, that the Indian govt.’s announcement of Special Incentives Package Scheme is likely to be followed by announcements by potential investors.

While SemIndia had already proposed investment in partnership with AMD, the latest one is from Hindustan Semiconductor Manufacturing Corporation (HSMC), a Silicon Valley-based semiconductor company. It has announced its plans to invest over $4 billion in chip foundries in India and has roped in Infineon as its technology partner; Infineon will license its 0.13u process techno and has said that it is open to considering an equity participation ‘subject to the final contract’.

According to a study by Frost and Sullivan, the semiconductor market in India is expected to grow from $3.25 billion in 2006 to $36 billion in 2015. The Indian govt. has announced Special Incentives Package Scheme, MoUs are being signed, what is to be seen now is the implementation of these plans and the coming up of the fabcities.

Read this article (Nadamuni says, in EE Times) ; Wanted to submit my comments there but looks like a perpetual error while submitting comments…..

2 issues which could be of concern to the fledgling Indian semiconductor market are: potential overcapacity situation and offering an attractive pricing strategy in face of strong competition from established regional foundries.

Investing with new equipment in light of the above and especially with the unavailability of incentives for such plants i.e. with second hand semiconductor equipment will make the potential investors wary.

However, having said that, if India were to offer the same set of incentives for second hand semicon equipment too, it’ll take a long time for it to catch up with cutting edge technology fabs as well as to address the design needs of the local design houses which have emerged from working on trailing edge technos to the leading edge ones.
Perhaps, a different set of incentives could work……???

UMC has announced that it plans to open a support office in Hyderabad, India. The main charter is to support India based customers. This is close on heels with TSMC’s setting up office in Bangalore, India.

There were some very interesting insights from the commentary on the panel discussion on the above topic.

People have been long talking about the demise of ASICs….and these are still around. A good starting point taken, hence, was the definition of ASICs itself. ASICs have undergone a transformation over the years and have evolved much from the traditional cell based ASICs.

Some interesting comments raised included:

- why have ASICs survived? Inspite of ridiculous prices, extremely unreliable and extremely unpredictable. Because they are needed. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing (Sherwani/OpenSilicon)
- Architecture is the key. More integration is not necessarily the right solution (Massabki/ChipX)
- How outsourcing and offshoring of basic R&D is affecting ASIC biz (Sherwani)

When we talk about ASICs declining, what are we referring to? Is it the number of design starts? And if so, which designs does this number include: cell based ASICs, embedded array, structured ASICs? Is it the total revenue?

Without a clear definition and specific measuring criteria, blanket statements do not make much sense.

Cisco and IBM are planning to develop a platform based on open standards to allow unified communications and collaborations in their applications. IBM will offer a set of application programming interfaces (APIs) as a subset of its Lotus Sametime collaboration software and Cisco will offer communication APIs for accessing voice and video services.
Cisco and IBM also will roll out “specific client offerings” based on the new platform and a set of “plug-ins” to combine the collaboration and unified communications capabilities of both companies.

I had written about the adoption of a similar approach in the EDA industry (Why can’t we do it in EDA). Especially with DFM and other UDSM challenges (and not to mention the standards’ war!), it is to the advantage of the designer if he can get the best of all tools in a unified integrated design flow. Since no single vendor can handle this on its own, a collaborative approach looks to be the best bet.

Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing noted in his presentation at the SPIE Advanced Lithography Conference last week that while there are some good point tools for DFM, integrated DFM solutions are still lacking.

As I noted in an earlier post, Why can’t we do it in EDA?, it is a huge task for a single vendor to handle even most of the important sources of variations through a single integrated flow. Integration of point tools requires standardization as well as agreement over interfaces and formats.

IBM’s Leon Stok had identified 4 eras in the EDA industry. For the 4th era i.e. design implementation platforms, he mentioned that we would need to define standards as APIs in order to allow tools to talk to each other.

The trend is moving more and more towards a hybrid approach

After several hiccups, India has announced its IC policy.

Dubbed the Special Incentive Package Scheme, the initiative is focused on attracting investments for setting up semiconductor plants and other technology manufacturing industries. Semiconductor companies seeking incentives—which will be 20 percent of the capital expenditure during the first 10 years—will have to invest a minimum $550 million, according to the plan.

The salient points were announced Feb. 22 with details to be out in the coming two weeks in a document that spells out the specifics about the level of equity, the interest-free component and other financial details.

This announcement is most likely to be followed by announcements by potential investors. AMD has already announced a technology pact with SemIndia Inc. for a semiconductor manufacturing facility in Hyderabad.

At least two more semiconductor manufacturing facilities are expected to be announced in the next few weeks, according to Raj Khare, chairman, India Semiconductor Association.
Samsung, Freescale, Motorola, Intel, Infineon, STMicrorelectronics and Toshiba are among the possible investors in a Rs.20,394 crore ($4.5 billion) manufacturing facility being set up by the Hindustan Semiconductor Manufacturing Corp. (HSMC) which is expected to establish a fabrication complex that will include several foundries to be built by HSMC. The fabs will 200- and 300mm wafer lines.

It has to be seen if and how the various consortiums as well as companies like Intel etc. tread on this “red carpet” rolled out by the Indian govt. And having decided to tread, it has to be seen which technology direction will these new fabs take up (as noted in my earlier post, “Vision Summit explores strategies driving semicon industry growth”)

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

Yet another company exits the Structured ASIC arena. After LSI Logic and then Synplicity, it’s now the turn of NEC. This is in line with a string of closures/layoffs and policy changes announced by Mr. Nakajima, NEC’s president.

NEC feels that Structured ASICs have not grown to a big biz yet and is risky to invest large resources in it. This is further aggravated when the company itself is not doing well overall.

Why is it that Structured ASICs hasn’t caught on? The general thinking when Structured ASICs evolved was that as long as there is the issue of high NREs and long design cycle time compounded by increasing risks involved with new designs/new techno/short market window etc., there will be a need to address the gap between FPGAs and Cell based ASICs. Structured ASICs definitely address this gap.

Could a possible reasoning be in the marketing strategy of Structured ASICs ??? As some one had pointed out a few years back……”Most of the companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against FPGAs. The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines’ lowest density is close to the highest density available in FPGA, there really isn’t much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn’t often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology”

ISA-Ernst & Young, India’s recently released report presents a snapshot of India’s semicon industry.
Some of the salient points are:
Talent quality: Moderate (US rated very high)
Talent Availability & scalability: Very Well (4th amongst peers, US rated 3rd )
Technical education quality: Moderate (rated 5th, US rated very high)
Talent cost advantage: Very well (Best along with China, US rated lowest)
Peer countries selected for study: Canada, China, Czech Republic, India, Israel, Taiwan, the United Kingdom and the United States

Other than the more prevalent known aspects as cited above, the report underscored a few interesting and vital points:
- India’s need to conceptualize & build products and move up the value chain
- Relatively lower level of electronics manufacturing which adversely impacts the semicon market potential
- Need to increase IP registration