Travelling On The Silicon Road

TSMC had recently unveiled its 65nm DFM compliance design support ecosystem by coming out with its DFM Data kit compiled with DFM Unified Format (DUF). DUF has been developed by TSMC to align DFM tools. This kit would help to put the fabless designers on an equal footing with the IDMs. The format, though, models only random and systematic defects with parametric defects being planned for a future release.

Now yet another tool has hit the “in news” DFM space.

Blaze DFM Inc recently rolled out its solution Blaze MO. It is marketed as targeting to improve the parametric yield through a better control over leakage, timing and variability.
It has an electrical focus in contrast with other DFM tools which have a geometric focus (focusing on wire spreading, lithography simulation and critical area analysis)

The heat is on…….

Thermal analysis is gaining momentum. While these analysis tools were there in the past especially with analog and mixed signal devices, they’ve lately gained prominence with sub 90nm digital designs too.

Thermal analysis tools track thermal gradients across the die. Uneven shifting of the threshold voltage, timing violations (clock timings are especially sensitive to delay variations caused by thermal gradients), leakage, electromigration, reliability are some of the thermal problems.

While some vendors are coming out with standalone thermal analysis tools e.g Gradient, some like Magma have thermal analysis in built into their power analysis tool as they believe that since power and temperature are interlinked, a user should not be shuttling between 2 separate analysis tools. As package plays a vital role in thermal analysis, some are getting package considerations also into the product.

Along with these tools, it’s the thermal management chips which are riding along the wave. According to Databeans, thermal management ICs could reach just under 2B$ in 5 years. The main growth segments cited are the ones using FPGAs and ASICs.

A snapshot analysis from IC Design Houses Survey 2006 (China and Taiwan) report done by EE Times

A. Revenues
a. 2005 revenues (expected)
Average 5.4 M$ in China, 9.2 M$ in Taiwan
China
15 M$ and above–19 %,1-2.9 M$ - 19%,less than 250 K$ and 3-6.9M-17%
Broadly uniformly distributed
Taiwan
15 M$ and above – 37%, less than 250 K$ - 16%, 7-10.9 M$ and
11 – 14.9 M$ - 11%
Taiwan has extremes; 15M$ category followed by b. 2006 revenues (forecasted)
China
15 M$ and above – 28% (a big jump from ’05)
Taiwan
15 M$ and above – 53% (a big jump with a marginal increase in the lower categories)
Basically, there is a broad and uniform representation by design houses in China for all categories – small to big. This is a reflection of several design houses appearing on China’s microelectronics landscape in the last few years. Taiwan, on the other hand, being more mature in this area has most of its design houses represented in the 15M$ category and then several smaller ones.

B. Applications
- Taiwan is predominantly desktop and Laptop computers followed by
handhelds and other consumer electronics.
- China has a more even spread across handhelds/PDAs, wireless consumers,
Cellular Wireless equipment & other telecom.
- Cellular/Wireless is more than LAN/WAN equipment in China; it’s the
reverse in Taiwan.
- China also has a higher percentage in Automotives which is a growing market
there.

C. Main difficulties when contracting foundries
China: Cycle time (54%) and cost (49%)
Taiwan: Cost (68%) and cycle time (45%)
Taiwan’s main application being Computing and Consumer Electronics which is a highly cost competitive market reflects this.

D. Design
a. Types
China
ASICs (66%), SoC (59%), Standard IC (29%), ASSP (8%) PLD/FPGA (17%)
Taiwan
ASICs (61%), SoC (53%), Standard IC (28%), ASSP (19%), PLD/FPGA (7%)

- Analog/Mixed signal designs to decrease in China while there is a
slight increase in Taiwan.
- China & Taiwan – Percentage of Digital ASICs as well as DSPs to
decrease, SoC will be more or less constant.
- Taiwan has more ASSPs, an indicator of the Consumer Electronics market
with consumer focused system designs that can be rapidly configured.
- Fewer newer designs are expected in 2006 but as revenues are
expected to increase, this may indicate more revenue/design in ’06
as compared from ‘05

b. Technology/Process
Average of 10 (Taiwan) and 8 (China) design projects in ’05 with
Digital design (Taiwan/China)
0.13um (11%/ 14%), 0.18um (48%/46%), 0.25u (11%/12%), 0.35u (15%/16%), 0.5-1.5u (15%/12%)
Analog design (Taiwan/China)
0.13um (2%/10%), 0.18um (32%/24%), 0.25u (11%/15%), 0.35u (22%/16%), 0.5-1.5u (24%/25%)

- 0.18um is the most frequently used technology in both countries.
- China has more designs in 0.13um both in analog and digital as compared
to Taiwan.
- Digital designs have more or less jumped from 0.35um to 0.18um with not
many in 0.25um. Analog/Mixed Signal designs are mostly in 0.5u and
above and in 0.18um

c. Gate Count in ASIC designs
Taiwan: 3 major blocks – Less than 50K, 100k to 299k and 1 to 2.49M
gates
China: More evenly spread. Bigger blocks are – 50k-99K, 500k to 999k,
1 to 2.49M gates

d. Challenges (Taiwan/China)
i. Reduction of design cycle time (60% / 60%)
Cycle time also figured highest for China under difficulties with foundries i.e. China’s biggest challenge is cycle time for both foundries as well as design cycle time while Taiwan has cost of foundries and design cycle time
ii. Reduction of design cost (51% / 46%)
iii. IP availability (23% / 23%)
iv. IP verification (18% / 16%)
v. DFT (5%/11%)
DFT figures higher in China. Can be attributed to higher gate complexity designs and types of designs (major applications - telecom equipment).
vi. Power Management (19% / 11%)
Power Management figures high in Taiwan after IP verification. This relates to the fact that Taiwan does a large chunk of designs for Consumer Electronics where power management is a major concern
vii. DFM (4%/ 1 %)
DFM figures higher in Taiwan. This may be attributed to the fact that the world’s top 2 foundries are from Taiwan. However, DFM is gaining momentum in sub micron technologies. So China with more designs moving to 0.13um as compared to Taiwan should have an equal if not higher figure for DFM under design challenges
viii. Design Iteration (5%/ 2%)
ix. Timing closure (5% / 2%)

E. Regional perspectives
IC design houses offer mostly Full system design followed by IP services. IP services is slightly higher in Taiwan w.r.t China (IP protection in China is a major concern and this reflected in the IP services numbers)

Gartner during it’s mid year update outlined 5 megatrends facing the industry - continued integration due to Moore’s Law, increasing cost and scale of manufacturing facilities, the role the consumer markets will have going forward, service providers of various kinds, and a set of new and potentially disruptive technologies.

One more major trend that I perceive, is increasing collaboration. Whether it is OEMs collaborating with service providers or EDA companies/Design houses with foundries, this collaboration will increase. This is especially true for deep sub micron technologies.

Fewer chip designs will also re-enforce EDA companies to rethink their strategies and biz models. They will need to address solutions. As pointed out by Robert Hum/Mentor Graphics, “it is time for a change”. For verification, for example, realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. An open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Technology innovations will continue, in fact grow faster. There will also be increase in the number of startups with each one of them trying to address some niche area in the market and trying to tap it in the mode they think best. However as pointed out by Gartner, the question is how many will survive the transitions.

Another outcome of fewer chip makers in the market due to increase in manufacturing scale will be the diminishing of manufacturing differentiation.

The market has moved more from standalone products to solutions. And solutions go hand in hand with service thus getting the service providers into a more prominent role. Service providers are nearer to the end customer and know their requirements which will also propel them towards a product defining role.

The growing power of the consumer market and keeping in mind its demands, will lead to more reconfigurable devices. The challenge, however, will be keeping the costs down as reconfigurability does not come with optimized silicon usage.

Yes, indeed the methodology should be done by people who know it best i.e. design engineers. EDA companies should step in to facilitate this and not formulate them. We should not have situations where the design engineer needs to grapple with firstly the design & process complexities and secondly with trying to fit the design tool into his design methodology. With the increasing complexities associated with sub micron designs, there is a need for more and more collaboration. The tasks are too mammoth and interlinked for any single entity to manage on their own. Realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. Indeed an open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Yes, it indeed is true that the real assets of a company are it’s intellectual capital. Not being tangible in the conventional manner, this is not analysed to the extent it merits.

Increasing your market share without upsetting your profit margin ; and all this while not letting your intellectual capital diminish is indeed a juggling act. While globalization pushes companies to compete internationally against lower paying work forces, it also throws open the option of getting work done not only cost effectively but also Qualitatively.

We start with a lean organization with the core people – the identified and nurtured intellectual capital. Identify all the work/activities which can be outsourced. Give it to smaller companies which focus on that specific activity. Tap on the freelancers specializing in niche areas. We do see this in the present scenario too e.g. design houses, foundries, testing, distributors etc. However, the synergy here needs to be channeled and optimized. With global work forces, anyhow geographical barriers are falling. It’s pay per usage. The core employees formulate the strategies, give directions for the company’s growth and manage this knowledge bank of smaller companies and free lance professionals.

There are quite a few challenges to this approach but I do not think they are unmanageable. The biggest one would be IP protection. But then, that hasn’t deterred much the design activities or technology development/transfer to places like China. The recent panel on IP in China moderated by the president of SIA and as reported in Electronics News by Suzanne Deffree (dt. 3/3/2006) cites - China has the intellectual capability and the numbers. Barriers are not going to work. We have to try to safely enable them.

Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.

DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.

With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.

Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty.

To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?

Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.

It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.

So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?

Mentors’ CEO Walden Rhines’ interview in Electronic Times (posted on 2/12/05) brought out 2 interesting points in the EDA industry :

First is on the EDA industry growth which Rhines attributes mainly to developing new solutions to new problems, developing new methodologies & applying technology to different applications. With a very small growth in the number of designers and with tools and methodology in place, design companies do not tend to spend so much in purchasing that many new licenses/seats.

The second interesting point is about start-ups. Usually started by professionals from the major EDA companies/design companies when they see issues/loops in the design flow which they feel they can plug in much better than the existing tools. With the market growing more and more towards point tools and now towards an open platform, they focus on a niche issue. While they contribute a little over 20% of the market revenue, they do represent a major chunk of the EDA methodologies mindshare. And excepting a few of them who have a solid business plan in addition to the strong technology base, most get acquired by the major EDA companies - and spur their growth.

While most other competitors foresee more growth in China, Cisco sees an edge in India and is investing heavily there. The things going for India include an unregulated economy, less competitive environment & a growing market . It’s worries in China include weaker IP protection laws and an edge to home grown local companies like Huawei, Harbor Networks etc. through loans and government support.

The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.

I read this paper, “Yield challenges require new DFM approach” by P.T Patel in EE Times. It’s very well written and informative.

Yet another pointer to making the existing design tools (the focus in the article was on routing) more suitable for getting your design manufacturable.

Quite an interesting article in Electronic Engineering Times by Richard Goering.

Getting to basics ….

In commercial space, a designer designs a chip with the objective that it should not only function as per specs but also be manufactured in a commercially viable mode. This is implicit. Else shouldn’t we have heard about tools like Design for Silicon Success/DFSS or DFFTSS….??

Yes, we do have flows which aim for FTSS but not point tools. The point tools facilitate various design phases like simulation, synthesis, routing etc. but it’s a design flow which optimizes their usage to achieve objectives like intended functionality , high yield. In fact, all the existing design tools should have this “DFM” embedded in them by default.

Designers need not become manufacturing experts and the tools should be good enough to handle the yield issues in a transparent and automatic manner. But with the mandatory breaking of walls between design and manufacturing in the DSM zone, it does help for the designer to be aware of the potential manufacturing issues and take them into account while designing in order to avoid corrections at later stages.

One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.

It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.

The sifting is being done……..

Unshackled IBM Microelectronics savors Game Box wins - a very interesting article by Ed Sperling in a special report, Movers & Shakers 2005, in Electronic Business online.

Lining up 3 top gaming platforms, Sony PlayStation 3, Microsoft Xbox 360 and the follow on to the Nintendo GameCube as customers for it’s Cell Processor is a real volume play. In the absence of any real killer application, high volumes design wins do not come easy.

Steven Longoria, vice president of semiconductor technology platforms in IBM’s Systems and Technology Group mentions that getting it’s technology consistent to avoid repetition of development steps is IBM’s top priority.

This is one area in the industry which usually takes a backseat amongst other priorities and is a major cause of ASIC design re spins. With the high mask costs, FTSS is getting more & more significant thus putting an ASIC vendor with a good track record of FTSS higher on the ASIC clients’ list. The shrinking market windows also do not leave much room for re spins.

Market research company, iSuppli Corp noted in a recent article posted in Electronic Engineering Times by Peter Clarke that India’s semiconductor design industry will nearly triple by 2010; it’s predicted to be 624M$ in ’05.

Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.

The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..

The microelectronics industry owes much to Moore’s Law – the number of transistors on a chip double every 2 years. It’s a principle which has been solid and consistent for the last 3 decades.

In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. “Because of Moore’s Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment.”

It’s an economic barometer with geometric scaling transforming to economic scaling.

Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.

It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.

And it has also led to the omnipresent question - after Moore’s Law, what ???

It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.

Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.

IBMs’ VC Group’s strategy outlines a varying and rewarding approach to the functioning of a ventures capital arm of a large company. Deviating from the well trodden path of investing cash for ROI, it is emphasizing more on relationships, interests’ alignment and development of a mutually supported ecosystem.

As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.

Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.

With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.

Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.

Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.