8th November 2012

WiFi standards - 802.11ac and 802.11ad/60 GHz

Recently, I was requested for some information on the Wi-Fi market landscape for 802.11ac and the 60GHz/802.11ad standards. I compiled a snippet and would like to share the same here too

Neither of the two standards has yet been ratified – expected next year. However, that has not deterred players from entering this market. Speculations on which standard prevails/dominates, transition path etc. abound. Both of them are geared for the mobile market – spanning across notebooks/ultra books and then smart phones. My take is that 802.11ac will be the mainstream while 802.11ad will co-exist for niche applications.

Comments, opinions welcome!

posted in Semiconductor, 802.11ad, 60 GHz, 802.11ac | 0 Comments

3rd July 2012

Fab Power

Looks like the scaling down road for fabless – foundry model is getting bumpier. First the high cost of setting up new fabs made the earlier IDMs get into the fab lite model – i.e. depend upon the pure play foundries for the basic process capacity and do the specialized process add-ons in-house to get the competitive advantage. The fabless companies too coupled with pure-play foundries and gained prominence. The industry seemed to have found a way out (at least temperoraliy) of the high cost challenges of scaling down coupled with the issues of designing multimillion gates chips with increasing features and decreasing time to market window.

But now the speed breakers on this road are getting frequent and higher. Take the last couple of examples. FD-SOI is one of the new transistor architectures thrown up by ST/ST-Ericsson for scaling down 28nm and below. The process is reported to give a 35% power performance gain and that too by a simpler process transition from the typical CMOS. But ST lacks the capacity and hence is exploring options with GlobalFoundries. The latter is reportedly insisting that it will use ST’s process to make parts for all other parties too, in exchange for this extra capacity – leading to ST/ST-E potentially losing on a big competitive edge of sole access to a proprietary process through its FD-SOI process.

The second recent example is of Qualcomm. The world’s largest fabless company uses TSMC‘s 28nm process to manufacture its Snapdragon S4. And the world’s largest pure play foundry has had yield/capacity issues on this node.

TSMC’s 28nm foundry capacity woes have put a dampener in the presently exclusive run of Qualcomm – the sole (at least presently) provider of integrated multimode 3G/4G LTE baseband chips. And it ripples further down the chain causing distress to LTE smartphone vendors. Shortage is not expected to cease before Q4’12. Qualcomm is now planning a 23 per cent increase in operating expenses this year and looking for alternative (apart from TSMC) suppliers. It’s CEO Paul Jacobs’s recent visit to Samsung, reportedly for discussions that included semiconductor supply as well as his comment of not ruling out owning the means of chip production has led to a lot of water cooler speculation.

Incidentally TSMC’s sales hit an all-time high (9.1% annual revenue growth) in April’12 – with much of the strong growth attributed by 28nm demand!

So where does this leave the fabless-foundry model? And how does this affect the IDMs?

One thing for sure is that the model will need to be tweaked in order to stand up to the sub 28nm/20nm challenges. Some pointers:

• Cost advantage of scaling down is diminishing for the foundries. The cost-per-transistor has been about 29% per node leading to cheaper scaled down chips. 28nm and sub has seen that levelling off for the foundries. Intel still has a big (at least a couple of years) lead in the process race. If the fabless companies do not see a steady decline in the cost-per-transistor in their foundries’ scaling, it certainly puts a spoke in their continuing down on the scaling path with this model.

• The prohibitive high cost of setting up a new fab and the related R&D and yield challenges just does not make sense for a fabless company, even Qualcomm, to start one. Owning a pre-planned and negotiated capacity or even production means with an existing foundry – yes but a fab from scratch, no, that doesn’t appear to be a viable option.

• With the increasing yield issues at smaller geometries pitched along with capacity shortage and uncertain market demand, a stronger vertical integration of supply chain may become the order of the day to sustain the fabless model – one which accounted for $64.9 billion in 2011. While expecting to resolve 28nm capacity shortage by Q4, TSMC has raised this year’s capex 42% to USD 8.5 billion to ride the market opportunities.

• Rewinding to one of my earlier blog posts (Jan 2008), I had cited a remark by Infineon’s CEO, Ziebart in an interview to EE Times’ rick Merritt, “The major thing giving semiconductor makers a competitive advantage has evaporated. Today everyone has access to the same process technology at roughly the same time. This access used to be what differentiated the best from the worst semiconductor companies, but now it has evaporated, What’s replacing process technology as a differentiator is systems know how, and it must be specific to a market area”. My comment to that, as also mentioned in the same post, was: Yes, the differentiator has moved from process technology; but it is due to access to the process techno. This access has become cost prohibitive for any single semiconductor company (perhaps leaving aside a couple with really deep pockets) and hence the scramble to find an alternate place in the value chain to survive.
That access to the process techno is now morphing, if not under threat.

• GlobalFoundties’ SVP Mojy Chian mentioned that “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market”. Now, does this mean that foundries will transition towards virtual IDMs?
Rewind to another earlier blog post (Dec 2007): “Over the last couple of years, we have seen IDMs going towards fablite and fabless models, and the emerging dominance of the original pure play foundries. I say “original” as lately these foundries are paving their way into newer territories like climbing up the design support value chain by increasing their IP portfolio, collaborating with EDA vendors for providing yield related data/information to the designers and reference design flows, and others – just short of coming up with their own ASSPs. So will we see the re-emergence of real IDMs albeit in the form of a morphed foundry??
IDMs, foundries, fabless… they are all morphing from their original identities and are reshaping the industry with their redefined (work in progress) grey and diffused boundaries

However, one thing stands tall amidst all this and that is “The “Fab power’ is increasingly getting honed into the semiconductor eco-system lately.” Fab matters

posted in Semiconductor, Process, Business, Foundry, Fabless, Technology, Samsung, Qualcomm, Intel, Ecosystem, chip design | 0 Comments

25th June 2012

Mediatek’s offer to buy MStar

Two compatriots for long at loggerheads have decided to join forces and take on the competition. News about Taiwanese chip designer MediaTek’s offer to buy rival MStar has created quite a buzz and water cooler speculation…. and of course the stock market. MStar was up 6.85 percent (maximum allowed in a session), while MediaTek gained 2.37 percent today.

My two cents’ worth addition to the buzz …..
- This acquisition will create the world’s fourth largest chip designer with total annual sales of US$4.2 billion in 2011

- The combined entity will have an almost 70% market share (a monopoly position??) in the TV SoC biz (DisplaySearch’s Q4’11 data put the two companies’ combined market share as 68.8%).

- Combined R&D resources and not looking over the shoulder for price cutting competition from the previous arch rivals can potentially sharpen the focus and product offering

- On the mobile phones arena: High end 3G smartphone chips along side the 2G ones for feature phones will consolidate & expand MediaTek’s mobile phone chip offering, especially in the emerging markets – more so in China where it has seen its once dominant position threatened by Spreadtrum and the likes (incidentally, MediaTek recently lost a TDSCDMA/WCDMA 3G chip socket in Samsung smartphone to Spreadtrum)

- And most importantly, it positions MediaTek well in an increasingly connected device market. With the growing convergence across platforms – TV, mobile phones, tablets/computing devices – it is crucial to integrate the relevant technologies across them so as to optimally and cost effectively leverage the same across the various platforms (Qualcomm announced a new Snapdragon for smart TVs and set top boxes in CES early this year and then at Computex later, it demonstrated its Smart TV reference platform with its quad-core Snapdragon S4 APQ8064 and MPQ8064 playing games and slinging TV frames. In E3 ’12 (Electronic Entertainment Expo), Samsung’s Smart TV included access to Nvidia’s new cloud gaming platform, GeForce Grid. Marvell too showcased its total solutions across Smart TVs, cloud computing and connectivity at Mobile World Congress)

- Concern: Talent retention/Integration of the combined work force. With almost 80% of MStar’s engineers doing the same work as folks at MediaTek, how will the parent entity avoid overlapping resources and address the potential loss (if not exodus) of talent?

posted in Semiconductor, Business, Communciation, Fabless, Industry Events, Mergers & Acquistions, 3G, MIDs, Samsung, Qualcomm, MediaTek, Spreadtrum, MStar | 0 Comments

20th April 2012

Chip designing and the cloud

One way to look at how chip designing can leverage from cloud computing is to look at the main benefits of cloud computing and project the same onto IC design. Obvious ones here are on demand access to computing power and data storage in a scalable mode. It is a capex to opex biz model.

 

Another way of looking at is to see what are the major challenges facing an IC designer and see how cloud computing can help. I personally find the second approach as one which if addressed properly will provide much compelling reasons for the chip design community to embrace the cloud; and optimally leverage from it.

 

Now I would not like to open the Pandora’s Box and vent on the numerous challenges that IC designers face…it will provide enough content for a separate article! But generally speaking,  amongst the various challenges an IC design engineer faces, a vital one is Design Methodology management and that includes two vital sub issues, (a)  Accelerating Turn Around Time and (b) Verification challenges. Can the cloud address these?

 

Let’s look into the first one i.e. Turn-around Time. Needless to say, this is one commodity which as a customer requirement is shrinking, especially for chips in the consumer applications. And the key entity here is the efficiency and effectiveness of the design flow. A point to clarify -  by design flow here, I am referring to the common design flow framework or the chip design methodology and not about the computing power and time (which are nevertheless key and can be addressed by cloud). This includes issues like design framework, EDA tools integration and biz model, efficient and safe design data transfer across databases etc.

 

The biggest challenge I see in a Design Framework for cloud is the feasibility of a standardized generic flow or a common design methodology/platform. Do customers have the motivation to re-architect their existing methodologies to take full advantage of cloud? Without such a flow, cloud will provide a computing ground for multiple jobs using multiple EDA tools i.e. we would be leveraging only on the computing power and storage from the cloud.

 

What will provide value-addition to this power-storage combo is a seamless design flow platform for the chip designer. This may be a standardized flow or a generic one with flexibility to include changes based on user needs – a replica of what a designer does in a “cloud less’ environment.

 

The second challenge here is the usage of multiple point tools (both from various EDA vendors as well as the in-house tools and scripts – something which experienced designers use quite a lot). Almost no one uses a single vendor flow nowadays. Let’s say we address this by multiple clouds, each cloud serving an EDA tool from a particular EDA vendor. This will involve movement of data across clouds in order to run multiple tools on the design database at various stages –giving rise to concerns on the huge data size and its security.

 

A likely solution to all this may be a unified GUI framework encompassing a generic seamless design flow with multiple point tools along with an easy to integrate various tweaks in the flow. This requires collaboration across EDA vendors and therein lies the third challenge – how does one get the EDA vendors to co-operate under a unified and a commercially viable biz model. Add to it, the point that users are not likely to pay for the complete menu of a unified design flow with multiple tools from multiple vendors (or for that matter even single EDA vendors). They will pay only for the tools as and when they use them. Collaboration, Licensing and viable biz models is key.

 

The next issue is Verification. With verification taking almost 60-70% of the total design time and its growing importance, this has become a major contributor to sleepless nights for the IC designers. - Verification concerns include handling of humungous data and that too with a highly iterative flow, requirement of high computing power as a sustainable expense, on a need be basis, scalable (different verification tasks require different hardware) and a limitless on demand compute time, high concurrent access and synchronization of databases, data integrity (need version control) and lastly efficient handling of batch jobs as well as interactive jobs.

 

Apart from Design Methodology management, a couple of other stormy points in the chip design cloud path are cloud ownership and secondly the security, data integrity and back-up.

I see cloud ownership as a vital component of chip design security in the cloud. After all, if I were to place my company’s most precious assets –i.e. my chip design database – on a cloud, I will definitely like to know as to who owns the cloud. And this is on top of my regular apprehensions about my data security, back up and related aspects.

 

Let me clarify – I am not talking here about the infra-structure provider e.g. Amazon and the likes. Rather it is the cloud framework/database owner. The framework here includes components of the existing physical eco-system integrated together – design database, EDA tools, user interface etc. – without which cloud computing will just service individual IC design tasks i.e. storage and processing power requirements; something which on its own is not exactly fully leveraging this powerful biz paradigm shift aka cloud computing.

 

So the question is - who will own the chip design cloud? Will it be the foundries (also cited as “natural design aggregators”), the EDA vendors, the fabless design companies or yet another entity? The reply gleaned from most of the stormy discussions elsewhere in the nimbus zone gravitates towards foundry.

 

In summary, cloud computing in chip design will be a big paradigm shift and is poised to bring about tremendous benefits to the design eco-system. However for the design community to actively adopt it, the relevant stake-holders need to look into it in a holistic way and much beyond the scalable and economic computing power and data storage combo.  And this may very well redefine the existing chip design methodology.

posted in Semiconductor, Business, Ecosystem, Cloud, chio design | 0 Comments

2nd March 2012

Elpida files for bankruptcy

The DRAM industry is not for the faint hearted. Add to the inherent “dynamic” nature of this biz, the waning of PC biz and onslaught of mobile tsunami and things definitely start gettimg pricklier.

Earlier this week, the Japanese DRAM maker, Elpida filed for bankruptcy. According to Q4 ’11 figures, Elpida had 12% of the market share, slightly trailing behind Micron (12.1%) and the top 2 players – Hynix (23.3%) and Samsung (44.3%).

Consolidation was waiting to happen in the DRAM space and now prices should hopefully stabilize. One company that does stand to gain here is Micron, the only non-Asian player in this market. It saw its shares rise on this news. A decade back, Micron walked away from a transaction under which it would have acquired the memory operations of South Korea’s Hynix Semiconductor. Now it has another opportunity where it can buy capacity cheaply (Elpida’s Hiroshima plant).

posted in Semiconductor, Business, DRAM, Elpida, Micron | 0 Comments

2nd March 2012

AMD acquires SeaMicro

AMD starts selling Intel based servers – it does make an intriguing catch phrase, correct?

AMD’s latest acquisition of SeaMicro has caused some ripples. SeaMicro is a US based exclusive start-up claiming high power and space reductions (both key factors in the server market). And it currently sells exclusively Intel based servers. Its technology includes a custom CPU (Atom or Xeon) + DRAM + Freedom Fabric ASIC.

AMD has seen its market share in the server market fall from 15% in 2007 to 6.5% in 2011. Add to it the fact that almost 22% of the company’s market share depends upon server sales. So, this acquisition will strengthen AMD’s stake in this sector.

Outlook here may well include – AMD phasing out Intel’s design/chips and replacing with its own (the thread performance of its CPUs score over Intel’s) or perhaps ARM (following its partners (IBM, Dell, HP) and…. at the mention of partners, with AMD selling chips to its existing partners and also selling servers which count these partners as competition, this acquisition can pose a channel conflict

posted in ASICs, Semiconductor, Business, Mergers & Acquistions, Intel, AMD, Server | 0 Comments

26th January 2012

Semiconductor Ecosystem

Recently a friend shared an interesting article, “Restoring American competitiveness” by Gary Pisano and Willy Shih & printed in HBR. While the article focuses on US, it does provide a deep insight and several pointers to the local Singapore context too.

Some of the points I especially liked were the description and importance of “industrial commons “(collective capabilities)” and its role in innovation and development of the ecosystem.

It is increasingly difficult for a company to be competitive in today’s dynamic and cut-throat markets. Being competitive in today’s market requires support of an “ecosystem” of all entities involved in the supply chain like suppliers, equipment makers, customers etc.

Now can an ecosystem be defined as a mere collection or presence of all relevant entities in the same geographical space? We do have several geographies with these entities together. But what is missing – and what turns this conglomeration to an ecosystem is a proactive and broad Collaboration across the entities. And this sort of collaboration is possible only when the users have a stake in the outcome.

And this leads me to ponder – whether Singapore has the ecosystem for the semiconductor industry. And if not, then what’s missing and how do we move towards it? Suggestions??

posted in Semiconductor, Business, Ecosystem | 0 Comments

25th January 2012

Capex disparity…. and the fortifications of the leaders

Add the 2012 planned capex spending of the world’s top two IDMs and you get an almost half of the total ’12 planned semiconductor capital expenditures. Add to it the world’s top pure play foundry’s planned capex and you end up with nearly thrice the amount the group spent in 2009.
This month saw a slew of capex announcements – Intel’s $12.1 to 12.9 billion, Samsung’s 1$2.2 billion and TSMC’s $6 billion; the first two an increase and the last a decrease (18%) from their 2011 capex numbers.

TSMC had already reported their plan to slash their 2012 capex in September last year. The major chunk of their capex this year will be spent on ramping up their 28nm process and their Gigafabs. Incidentally, 28nm accounted for 2% of TSMC’s 2011 revenues while 40nm and 65nm accounted for 27% and 30% each. And remember, they had an oversupply on 65nm capacity while seeing a demand exceeding supply on 28nm. TSMC’s 2012 outlook – a challenging year.

Intel and Samsung have a lot at stake in the mobile internet devices (MID) market. Intel is betting high on its ultrabooks while Samsung owes much of its lucrative foundry biz to Apple. In addition, it is aggressively ramping up for its in-house application processor to ride on the surging MIDs wave.

These two have an advantage of their in-house designs to test and ramp up on leading edge processes while the pure play foundries like TSMC rely much on their customers’ designs for this.

One thing that is getting increasingly visible – the chasm between the leaders and the ROP (Rest of Pack) is steadily increasing. While this beckons consolidation, it also serves as an innovation catalyst for the smaller but niche companies and strategies emerging in and filling this gap.

posted in Semiconductor, Business, Foundry, MIDs, Intel | 0 Comments

14th January 2012

A 2011 snapshot of the Semiconductor Business

This is the time of the year when the digital cooler is abuzz with the gazing into the crystal ball.
Here I take a look at what all that happened in the semiconductor space in the year just gone past….
for is it not the past that also paves the way the New Year pans out?

A snippet into the year that’s just gone and an usher for the next one…. with an Asia-Pacific region focus
A 2011 snapshot of the Semiconductor Business

posted in Semiconductor, Business, Samsung, Qualcomm, MediaTek, Spreadtrum, MStar, Intel | 0 Comments

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